The Phase Frequency Detector (PFD) of the PLL takes inputs from the reference path and the feedback divider output and produces an output that is dependent on the phase and frequency difference between the two inputs. The input frequency of the PFD is equal to the 50-MHz reference frequency doubled if the reference doubler is enabled and then divided by 4 if the reference divider is enabled. The feedback frequency to the PFD must equal the reference path frequency to the PFD for the PLL to lock.