8.4.2.2 Fine Frequency Margining

IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock compensation.

To prevent such overflow and underflow errors from occurring, modern ASICs and FPGAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 27, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3. The LMK61E08 provides the ability to fine tune the frequency of its outputs based on changing its load capacitance for the integrated oscillator. This fine tuning can be done through I²C as described in Integrated Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E08 undergoes a smooth monotonic change in frequency.