ZHCSE74B September   2015  – February 2017 LMK61E2

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 ADD Input Characteristics
    11. 6.11 Frequency Tolerance Characteristics
    12. 6.12 Power-On/Reset Characteristics (VDD)
    13. 6.13 I2C-Compatible Interface Characteristics (SDA, SCL)
    14. 6.14 PSRR Characteristics
    15. 6.15 Other Characteristics
    16. 6.16 PLL Clock Output Jitter Characteristics
    17. 6.17 Typical 156.25-MHz Output Phase Noise Characteristics
    18. 6.18 Typical 161.1328125 MHz Output Phase Noise Characteristics
    19. 6.19 Additional Reliability and Qualification
    20. 6.20 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Circuitry
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 EEPROM Map
    7. 8.7 Register Map
      1. 8.7.1 Register Descriptions
        1. 8.7.1.1  VNDRID_BY1 Register; R0
        2. 8.7.1.2  VNDRID_BY0 Register; R1
        3. 8.7.1.3  PRODID Register; R2
        4. 8.7.1.4  REVID Register; R3
        5. 8.7.1.5  SLAVEADR Register; R8
        6. 8.7.1.6  EEREV Register; R9
        7. 8.7.1.7  DEV_CTL Register; R10
        8. 8.7.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.7.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.7.1.10 DIFFCTL Register; R21
        11. 8.7.1.11 OUTDIV_BY1 Register; R22
        12. 8.7.1.12 OUTDIV_BY0 Register; R23
        13. 8.7.1.13 PLL_NDIV_BY1 Register; R25
        14. 8.7.1.14 PLL_NDIV_BY0 Register; R26
        15. 8.7.1.15 PLL_FRACNUM_BY2 Register; R27
        16. 8.7.1.16 PLL_FRACNUM_BY1 Register; R28
        17. 8.7.1.17 PLL_FRACNUM_BY0 Register; R29
        18. 8.7.1.18 PLL_FRACDEN_BY2 Register; R30
        19. 8.7.1.19 PLL_FRACDEN_BY1 Register; R31
        20. 8.7.1.20 PLL_FRACDEN_BY0 Register; R32
        21. 8.7.1.21 PLL_MASHCTRL Register; R33
        22. 8.7.1.22 PLL_CTRL0 Register; R34
        23. 8.7.1.23 PLL_CTRL1 Register; R35
        24. 8.7.1.24 PLL_LF_R2 Register; R36
        25. 8.7.1.25 PLL_LF_C1 Register; R37
        26. 8.7.1.26 PLL_LF_R3 Register; R38
        27. 8.7.1.27 PLL_LF_C3 Register; R39
        28. 8.7.1.28 PLL_CALCTRL Register; R42
        29. 8.7.1.29 NVMSCRC Register; R47
        30. 8.7.1.30 NVMCNT Register; R48
        31. 8.7.1.31 NVMCTL Register; R49
        32. 8.7.1.32 MEMADR Register; R51
        33. 8.7.1.33 NVMDAT Register; R52
        34. 8.7.1.34 RAMDAT Register; R53
        35. 8.7.1.35 NVMUNLK Register; R56
        36. 8.7.1.36 INT_LIVE Register; R66
        37. 8.7.1.37 SWRST Register; R72
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Jitter Considerations in Serdes Systems
      2. 9.2.2 Frequency Margining
        1. 9.2.2.1 Fine Frequency Margining
        2. 9.2.2.2 Coarse Frequency Margining
      3. 9.2.3 Design Requirements
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 Custom Design With WEBENCH® Tools
          2. 9.2.3.1.2 Device Selection
          3. 9.2.3.1.3 VCO Frequency Calculation
          4. 9.2.3.1.4 Device Configuration
          5. 9.2.3.1.5 PLL Loop Filter Design
          6. 9.2.3.1.6 Spur Mitigation Techniques
            1. 9.2.3.1.6.1 Phase Detection Spur
            2. 9.2.3.1.6.2 Integer Boundary Fractional Spur
            3. 9.2.3.1.6.3 Primary Fractional Spur
            4. 9.2.3.1.6.4 Sub-Fractional Spur
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 使用 WEBENCH® 工具定制设计方案
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Parameter Measurement Information

7.1 Device Output Configurations

LMK61E2 lvpecl_output_dc_configuration_snas674.gif Figure 16. LVPECL Output DC Configuration During Device Test
LMK61E2 lvds_output_dc_configuration_snas674.gif Figure 17. LVDS Output DC Configuration During Device Test
LMK61E2 hcsl_output_dc_configuration_snas674.gif Figure 18. HCSL Output DC Configuration During Device Test
LMK61E2 lvpecl_output_ac_configuration_snas677.gif Figure 19. LVPECL Output AC Configuration During Device Test
LMK61E2 lvds_output_ac_configuration_snas677.gif Figure 20. LVDS Output AC Configuration During Device Test
LMK61E2 hcsl_output_ac_configuration_snas677.gif Figure 21. HCSL Output AC Configuration During Device Test
LMK61E2 psrr_test_setup_snas674.gif Figure 22. PSRR Test Setup
LMK61E2 differential_output_voltage_rise_fall_time_snas674.gif Figure 23. Differential Output Voltage and Rise/Fall Time
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