ZHCSEB9A October   2015  – November 2015 LMK61PD0A2

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Control
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Power Supply
    6. 7.6  LVPECL Output Characteristics
    7. 7.7  LVDS Output Characteristics
    8. 7.8  HCSL Output Characteristics
    9. 7.9  OE Input Characteristics
    10. 7.10 OS, FS[1:0] Input Characteristics
    11. 7.11 Frequency Tolerance Characteristics
    12. 7.12 Power-On/Reset Characteristics (VDD)
    13. 7.13 PSRR Characteristics
    14. 7.14 PLL Clock Output Jitter Characteristics
    15. 7.15 Additional Reliability and Qualification
    16. 7.16 Typical Performance Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Block-Level Description
      2. 9.3.2 Device Configuration Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Jitter Considerations in Serdes Systems
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
  13. 13器件和文档支持
    1. 13.1 社区资源
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Device Control

Table 1. Output Frequency Mapping for FS[1:0] Selection

FS1 FS0 OUT FREQUENCY (MHz) RELEVANT STANDARDS
0 0 100 PCI Express
0 NC 312.5 10 Gbps Ethernet
0 1 125 1 Gbps Ethernet
NC 0 106.25 Fiber Channel
NC NC 156.25 10 Gbps Ethernet
NC 1 212.5 Fiber Channel
1 0 62.5 1 Gbps Ethernet
1 NC Reserved n/a
1 1 Reserved n/a

Table 2. Output Type Mapping for OS, OE Selection

OS OE OUTPUT TYPE
X 0 Disabled (PLL functional)
0 1 LVPECL
NC 1 LVDS
1 1 HCSL
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |