ZHCSEB9A October   2015  – November 2015 LMK61PD0A2

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Control
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Power Supply
    6. 7.6  LVPECL Output Characteristics
    7. 7.7  LVDS Output Characteristics
    8. 7.8  HCSL Output Characteristics
    9. 7.9  OE Input Characteristics
    10. 7.10 OS, FS[1:0] Input Characteristics
    11. 7.11 Frequency Tolerance Characteristics
    12. 7.12 Power-On/Reset Characteristics (VDD)
    13. 7.13 PSRR Characteristics
    14. 7.14 PLL Clock Output Jitter Characteristics
    15. 7.15 Additional Reliability and Qualification
    16. 7.16 Typical Performance Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Block-Level Description
      2. 9.3.2 Device Configuration Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Jitter Considerations in Serdes Systems
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
  13. 13器件和文档支持
    1. 13.1 社区资源
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Device Supply Voltage -0.3 3.6 V
VIN Output Voltage Range for Logic Inputs -0.3 VDD + 0.3 V
VOUT Output Voltage Range for Clock Outputs -0.3 VDD + 0.3 V
TJ Junction Temperature 150 °C
TSTG Storage Temperature -40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Device Supply Voltage 3.135 3.3 3.465 V
TA Ambient Temperature -40 25 85 °C
TJ Junction Temperature 125 °C
tRAMP VDD Power-Up Ramp Time 0.1 100 ms

7.4 Thermal Information

THERMAL METRIC(1) LMK61PD0A2 (2) (3) (4) UNIT
QFM (SIA)
8 PINS
Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400
RθJA Junction-to-ambient thermal resistance 54 44 41.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34 n/a n/a
RθJB Junction-to-board thermal resistance 36.7 n/a n/a
ψJT Junction-to-top characterization parameter 11.2 16.9 21.9
ψJB Junction-to-board characterization parameter 36.7 37.8 38.9
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated on a 4 layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality.

7.5 Electrical Characteristics - Power Supply(1)

VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Device Current Consumption LVPECL(2) 162 208 mA
LVDS 152 196
HCSL 155 196
IDD-PD Device Current Consumption when output is disabled OE = GND 136
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.

7.6 LVPECL Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency(2) 62.5 312.5 MHz
VOD Output Voltage Swing
(VOH - VOL)(2)		 700 800 1200 mV
VOUT, DIFF, PP Differential Output Peak-to-Peak Swing 2 x |VOD| V
VOS Output Common Mode Voltage VDD – 1.55 V
tR / tF Output Rise/Fall Time (20% to 80%)(3) 120 200 ps
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) 156.25 MHz -165 dBc/Hz
ODC Output Duty Cycle(3) 45% 55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.

7.7 LVDS Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency(1) 62.5 312.5 MHz
VOD Output Voltage Swing
(VOH - VOL)(1)		 300 390 480 mV
VOUT, DIFF, PP Differential Output Peak-to-Peak Swing 2 x |VOD| V
VOS Output Common Mode Voltage 1.2 V
tR / tF Output Rise/Fall Time (20% to 80%)(2) 150 250 ps
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) 156.25 MHz -162 dBc/Hz
ODC Output Duty Cycle(2) 45% 55%
ROUT Differential Output Impedance 125 Ohm
(1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(2) Ensured by characterization.

7.8 HCSL Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency 62.5 312.5 MHz
VOH Output High Voltage 600 850 mV
VOL Output Low Voltage -100 100 mV
VCROSS Absolute Crossing Voltage(2)(3) 250 475 mV
VCROSS-DELTA Variation of VCROSS(2)(3) 0 140 mV
dV/dt Slew Rate(4) 0.8 2 V/ns
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) 100 MHz -164 dBc/Hz
ODC Output Duty Cycle(4) 45% 55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing.
(3) Ensured by design.
(4) Ensured by characterization.

7.9 OE Input Characteristics

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage 1.4 V
VIL Input Low Voltage 0.6 V
IIH Input High Current VIH = VDD -40 40 uA
IIL Input Low Current VIL = GND -40 40 uA
CIN Input Capacitance 2 pF

7.10 OS, FS[1:0] Input Characteristics

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage 1.4 V
VIL Input Low Voltage 0.4 V
IIH Input High Current VIH = VDD -40 40 uA
IIL Input Low Current VIL = GND -40 40 uA
CIN Input Capacitance 2 pF

7.11 Frequency Tolerance Characteristics(1)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fT Total Frequency Tolerance All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) -50 50 ppm
(1) Ensured by characterization.

7.12 Power-On/Reset Characteristics (VDD)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTHRESH Threshold Voltage(1) 2.72 2.95 V
VDROOP Allowable Voltage Droop(2) 0.1 V
tSTARTUP Startup Time (1) Time elapsed from VDD at 3.135 V to output enabled 10 ms
tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 us
tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 us
(1) Ensured by characterization.
(2) Ensured by design.

7.13 PSRR Characteristics(1)

VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PSRR Spurs Induced by 50 mV Power Supply Ripple(2)(3) at 156.25 MHz output, all output types Sine wave at 50 kHz -70 dBc
Sine wave at 100 kHz -70
Sine wave at 500 kHz -70
Sine wave at 1 MHz -70
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
(3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.

7.14 PLL Clock Output Jitter Characteristics(1)(3)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RJ RMS Phase Jitter(2)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)		 fOUT ≥ 100 MHz, All output frequencies and output types 100 200 fs RMS
RJ RMS Phase Jitter(2)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)		 fOUT = 62.5 MHz, All output frequencies and output types 200 400 fs RMS
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Ensured by characterization.
(3) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

7.15 Additional Reliability and Qualification

PARAMETER CONDITION / TEST METHOD
Mechanical Shock MIL-STD-202, Method 213
Mechanical Vibration MIL-STD-202, Method 204
Moisture Sensitivity Level J-STD-020, MSL3

7.16 Typical Performance Characteristics

LMK61PD0A2 D001_SNAS674.png Figure 1. Phase Noise of LVPECL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = GND
LMK61PD0A2 D003_SNAS674.png Figure 3. Phase Noise of HCSL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = VDD
LMK61PD0A2 D017_SNAS675.gif Figure 5. LVDS Differential Output Swing vs Frequency
LMK61PD0A2 D002_SNAS674.png Figure 2. Phase Noise of LVDS Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = NC
LMK61PD0A2 D016_SNAS675.gif Figure 4. LVPECL Differential Output Swing vs Frequency
LMK61PD0A2 D018_SNAS675.gif Figure 6. HCSL Differential Output Swing vs Frequency
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