LMKDB11xx are DB2000QL compliant clock buffers that distribute either 20 (LMKDB1120), or 8 (LMKDB1108) LP-HCSL clocks (respectively) designed for PCIe Gen 1 through 6 applications. LMKDB12xx are DB2000QL compliant clock muxes that can distribute 4 (LMKDB1204) and 2 (LMKDB1202) LP-HCSL clock outputs from two clock input sources.

With ultra-low additive jitter and ultra-low propagation delay, both devices allow for enough jitter margin for the entire clock path mainly required for PCIe Gen 5 and Gen 6 buffer cascading and Ethernet fan-out applications. The LMKDB11xx and LMKDB12xx also support both 1.8 V and 3.3 V supply voltages for better design flexibility.

LMKDB11xx and LMKDB12xx have individual OE controls for all outputs, which provides more design flexibility. Each output of each device also has programmable slew rate, programmable output amplitude swing, and automatic output disable. The devices support 100-Ω or 85-Ω LP-HCSL, denoted by the part number as shown in Section 4, with output frequencies of up to 400 MHz. LMKDB12xx devices have ZOUT_SEL pin to select 100-Ω or 85-Ω LP-HCSL output impedance.

LMKDB11xx have pin mode, SMBus mode, and Side Band Interface (SBI) mode, which can all be used at the same time. While LMKDB12xx only offers pin mode and SMBus mode. The vSMB_EN pin on LMKDB12xx can be used to select pin mode or SMBus mode. SBI enables or disables output clocks at a much faster speeds (up to 25 MHz) as compared to SMBus. Furthermore, because both SBI and SMBus can operate at the same time, SMBus can still be used to take over device control and readback status after power-up. For more details please refer to Section 8.4

Refer to Section 8 for the detailed descriptions of the devices pins and the Register Map for more details on the device registers.