In the recommended power down sequence, PWRDN# is asserted while input clocks are valid. Make sure to hold the PWRDN# pin at low level for two consecutive rising edges of the input clock cycle. As a result, all clock outputs are muted to low/low (OUTx_P = Low, OUTx_N = Low) without a glitch. Following any other sequence brings the device to an undefined mode and can cause glitches or invalid outputs.