ZHCSFR2B December   2016  – March 2018 LMR23630-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与负载间的关系，VIN = 12V，PFM 选项
  4. 4 修订历史记录
  5. 5 Product Portfolio
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 8.3.2  Adjustable Frequency
      3. 8.3.3  Adjustable Output Voltage
      4. 8.3.4  Enable/Synchronization
      5. 8.3.5  VCC, UVLO
      6. 8.3.6  Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
      7. 8.3.7  Power Good (PGOOD)
      8. 8.3.8  Internal Compensation and CFF
      9. 8.3.9  Bootstrap Voltage (BOOT)
      10. 8.3.10 Overcurrent and Short-Circuit Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light Load Operation (PFM Option)
      5. 8.4.5 Light Load Operation (FPWM Option)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Output Voltage Setpoint
        3. 9.2.2.3  Switching Frequency
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Feed-Forward Capacitor
        7. 9.2.2.7  Input Capacitor Selection
        8. 9.2.2.8  Bootstrap Capacitor Selection
        9. 9.2.2.9  VCC Capacitor Selection
        10. 9.2.2.10 UVLO Setpoint
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Considerations
      3. 11.1.3 Feedback Resistors
    2. 11.2 Layout Examples
  12. 12器件和文档支持
    1. 12.1 使用 WEBENCH® 工具创建定制设计
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VIN PIN)
VIN Operation input voltage 4 36 V
VIN_UVLO Undervoltage lockout thresholds Rising threshold 3.3 3.7 3.9 V
Falling threshold 2.9 3.3 3.5
ISHDN Shutdown supply current VEN = 0 V, VIN = 12 V, TJ = –40°C to 125°C 2 4 μA
IQ Operating quiescent current (non- switching) VIN = 12 V, VFB = 1.1 V, TJ = –40°C to 125°C, PFM mode 75 μA
ENABLE (EN/SYNC PIN)
VEN_H Enable rising threshold voltage 1.4 1.55 1.7 V
VEN_HYS Enable hysteresis voltage 0.4 V
VWAKE Wake-up threshold 0.4 V
IEN Input leakage current at EN pin VIN = 4 V to 36 V, VEN= 2 V 10 100 nA
VIN = 4 V to 36 V, VEN= 36 V 1 μA
VOLTAGE REFERENCE (FB PIN)
VREF Reference voltage VIN = 4 V to 36 V, TJ = 25°C 0.985 1 1.015 V
VIN = 4 V to 36 V, TJ = –40°C to 125°C 0.98 1 1.02
ILKG_FB Input leakage current at FB pin VFB= 1 V 10 nA
POWER GOOD (PGOOD PIN) WSON Only
VPG_OV Power-good flag overvoltage tripping threshold % of reference voltage 104% 107% 110%
VPG_UV Power-good flag undervoltage tripping threshold % of reference voltage 92% 94% 96.5%
VPG_HYS Power-good flag recovery hysteresis % of reference voltage 1.5%
VIN_PG_MIN Minimum VIN for valid PGOOD output 50 μA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C 1.5 V
VPG_LOW PGOOD low level output voltage 50 μA pullup to PGOOD pin, VIN = 1.5 V, VEN = 0 INV 0.4 V
0.5 mA pullup to PGOOD pin, V =13.5 V, VEN = 0 V 0.4
INTERNAL LDO (VCC PIN)
VCC Internal LDO output voltage 4.1 V
VCC_UVLO VCC undervoltage lockout thresholds Rising threshold 2.8 3.2 3.6 V
Falling threshold 2.4 2.8 3.2
CURRENT LIMIT
IHS_LIMIT Peak inductor current limit HSOIC package 3.8 5 6.2 A
WSON package 4 5.5 6.6
ILS_LIMIT Valley inductor current limit HSOIC package 2.9 3.6 4.6 A
WSON package 2.9 3.6 4.2
IL_ZC Zero cross current limit –0.04 A
IL_NEG Negative current limit (FPWM option) –2.7 –2 –1.3 A
INTEGRATED MOSFETS
RDS_ON_HS High-side MOSFET ON-resistance HSOIC package, VIN = 12 V, IOUT = 1 A 185 mΩ
WSON package, VIN = 12 V, IOUT = 1 A 160
RDS_ON_LS Low-side MOSFET ON-resistance HSOIC package, VIN = 12 V, IOUT = 1 A 105 mΩ
WSON package, VIN = 12 V, IOUT = 1 A 95
THERMAL SHUTDOWN
TSHDN Thermal shutdown threshold 162 170 178 °C
THYS Hysteresis 15 °C
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