8.3.4 Enable/Synchronization

The voltage on the EN pin controls the ON or OFF operation of LMR23630-Q1. A voltage less than 1 V (typical) shuts the device down while a voltage higher than 1.6 V (typical) is required to start the regulator. The EN/SYNC pin is an input and cannot be left open or floating. The simplest way to enable the operation of the LMR23630-Q1 is to connect the EN to V_IN. This allows self-start-up of the LMR23630-Q1 when V_IN is within the operation range.

Many applications benefit from the employment of an enable divider R_ENT and R_ENB (Figure 16) to establish a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing and protection.

Figure 16. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at the EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100ns (typ). A 3.3 V or a higher amplitude pulse signal coupled through a 1 nF capacitor C_SYNC is a good starting point. Keeping R_ENT // R_ENB (R_ENT parallel with R_ENB) in the 100-kΩ range is a good choice. R_ENT is required for this synchronization circuit, but R_ENB can be left unmounted if system UVLO is not needed. LMR23630-Q1 switching action can be synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 18 and Figure 19 show the device synchronized to an external system clock.

Figure 17. Synchronize to External Clock

Figure 18. Synchronizing in PWM Mode

Figure 19. Synchronizing in PFM Mode