Every switching regulator has a minimum controllable on time dictated by the inherent delays and blanking times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend the minimum controllable duty cycle, the LMR336x0AP-Q1 automatically reduces the switching frequency when the minimum on time limit is reached. This way the converter can regulate the lowest programmable output voltage at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before frequency foldback occurs is found in Equation 2. The values of t_ON and f_SW can be found in Section 7.5. As the input voltage is increased, the switch on time (duty-cycle) reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops, while the on time remains fixed. This relationship is highlighted in Figure 8-13 for a nominal switching frequency of 2.1 MHz.

Equation 2.

Figure 8-13 Switching Frequency vs Input Voltage V_OUT = 3.3 V