ZHCSJO4A May 2019 – October 2019 LMR34206-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN PIN) | ||||||
IQ-nonSW | Operating quiescent current (non-switching)(2) | VEN = 3.3 V (PFM variant only) | 14 | 24 | 35 | µA |
ISD | Shutdown quiescent current; measured at VIN pin | VEN = 0 V | 3.3 | µA | ||
ENABLE (EN PIN) | ||||||
VEN-VCC-H | Enable input high level for VCC output | VENABLE rising; Internal LDO turns ON | 1.14 | V | ||
VEN-VCC-L | Enable input low level for VCC output | VENABLE falling; Internal LDO turns OFF | 0.3 | V | ||
VEN-VOUT-H | Enable input high level for VOUT | VENABLE rising; Switching ON | 1.157 | 1.231 | 1.3 | V |
VEN-VOUT-HYS | Enable input hysteresis for VOUT | Hysteresis below VEN-VOUT-H; Switching OFF | 45 | 110 | 175 | mV |
ILKG-EN | Enable input leakage current | VEN = 3.3V | 0.2 | 50 | nA | |
INTERNAL LDO (VCC PIN) | ||||||
VCC | Internal VCC voltage | 6 V ≤ VIN ≤ 42 V | 4.75 | 5 | 5.25 | V |
VCC-UVLO-Rising | Internal VCC undervoltage lockout | VCC rising | 3.6 | 3.8 | 4.0 | V |
VCC-UVLO-Falling | Internal VCC undervoltage lockout | VCC falling | 3.1 | 3.3 | 3.5 | V |
VOLTAGE REFERENCE (FB PIN) | ||||||
V5v0-Fixed | 5 V Fixed Output voltage | Fixed output voltage option | 4.9 | 5 | 5.1 | V |
V3v3-Fixed | 3.3 V Fixed Output voltage | Fixed output voltage option | 3.23 | 3.3 | 3.37 | V |
ILKG-5v0-Fixed | Feedback leakage current; 5v0 Fixed | VOUT = 5 V (Fixed output voltage option only) | 2.5 | 2.9 | µA | |
ILKG-3v3V-Fixed | Feedback leakage current; 3v3 Fixed | VOUT = 3.3 V (Fixed output voltage option only) | 1.4 | 1.8 | µA | |
CURRENT LIMITS AND HICCUP | ||||||
ISC | High-side current limit(3) | 0.8 | 1 | 1.2 | A | |
ILS-LIMIT | Low-side current limit(3) | 0.6 | 0.8 | 0.95 | A | |
IL-ZC | Zero cross detector threshold | PFM variants only | 0.02 | A | ||
IPEAK-MIN | Minimum inductor peak current(3) | 0.18 | A | |||
IL-NEG | Negative current limit(3) | FPWM variant only | -0.95 | –0.6 | –0.25 | A |
POWER GOOD (PGOOD PIN) | ||||||
VPG-HIGH-UP | Power-Good upper threshold - rising | % of FB voltage | 105% | 107% | 110% | |
VPG-LOW-DN | Power-Good lower threshold - falling | % of FB voltage | 90% | 93% | 95% | |
VPG-HYS | Power-Good hysteresis (rising & falling) | % of FB voltage | 2% | |||
TPG | Power-Good rising/falling edge deglitch delay | 80 | 140 | 200 | µs | |
VPG-VALID | Minimum input voltage for proper Power-Good function | 2 | V | |||
RPG | Power-Good on-resistance | VEN = 2.5 V | 80 | 165 | Ω | |
RPG | Power-Good on-resistance | VEN = 0 V | 35 | 90 | Ω | |
OSCILLATOR | ||||||
FOSC | Internal oscillator frequency | 2.1-MHz variant | 1.95 | 2.1 | 2.35 | MHz |
MOSFETS | ||||||
RDS-ON-HS | High-side MOSFET ON-resistance | IOUT = 0.5 A | 225 | 435 | mΩ | |
RDS-ON-LS | Low-side MOSFET ON-resistance | IOUT = 0.5 A | 150 | 280 | mΩ |