ZHCSI00D April 2018 – September 2020 LMR36015
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1
Design 1: Low Power 24-V, 1.5-A PFM Converter
- 10.2.1.1 Design Requirements
- 10.2.1.2
Detailed Design Procedure
- 10.2.1.2.1 Custom Design With WEBENCH Tools
- 10.2.1.2.2 Choosing the Switching Frequency
- 10.2.1.2.3 Setting the Output Voltage
- 10.2.1.2.4 Inductor Selection
- 10.2.1.2.5 Output Capacitor Selection
- 10.2.1.2.6 Input Capacitor Selection
- 10.2.1.2.7 CBOOT
- 10.2.1.2.8 VCC
- 10.2.1.2.9 CFF Selection
- 10.2.1.2.10 Maximum Ambient Temperature
- 10.2.2 Application Curves
- 10.2.3 Design 2: High Density 24-V, 1.5-A FPWM Converter
- 10.2.1
Design 1: Low Power 24-V, 1.5-A PFM Converter
- 10.3 What to Do and What Not to Do
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
10.2.1.2.5 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient performance. The output capacitor bank is usually limited by the load transient requirements rather than the output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an upper bound on the ESR, required to meet a specified load transient.
where
- ΔVOUT = output voltage transient
- ΔIOUT = output current transient
- K = ripple factor from Section 10.2.1.2.4
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the output voltage ripple.
where
- Vr = peak-to-peak output voltage ripple
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple requirements.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.