ZHCSKN9B December 2019 – December 2022 LMR36506
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Enable, Start-up, and Shutdown
- 8.3.2 Adjustable Switching Frequency (with RT)
- 8.3.3 Power-Good Output Operation
- 8.3.4 Internal LDO, VCC UVLO, and VOUT/BIAS Input
- 8.3.5 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Terminal)
- 8.3.6 Output Voltage Selection
- 8.3.7 Soft Start and Recovery from Dropout
- 8.3.8 Current Limit and Short Circuit
- 8.3.9 Thermal Shutdown
- 8.3.10 Input Supply Current
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 9.3 Best Design Practices
- 9.4 Power Supply Recommendations
- 9.5 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.4.3.2.2 Frequency Reduction
The LMR36506 reduces frequency whenever output voltage is high. This function is enabled whenever the internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded.
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.