SNVSCH7 February 2024 LMR38025
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency Peak Current Mode Control
- 7.3.2 Adjustable Output Voltage
- 7.3.3 Enable
- 7.3.4 Switching Frequency and Synchronization (RT/SYNC)
- 7.3.5 Power-Good Flag Output
- 7.3.6 Minimum On Time, Minimum Off Time, and Frequency Foldback
- 7.3.7 Bootstrap Voltage
- 7.3.8 Overcurrent and Short-Circuit Protection
- 7.3.9 Soft Start
- 7.3.10 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 DRR Package, 12-Pin WSON (Top View)Table 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 1, 2 | G | Power and analog ground terminal. All electrical parameters are measured with respect to this pin. Connect a high-quality bypass capacitor directly to this pin and VIN with short and wide traces. |
| EN | 3 | A | Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float. |
| NC | 4 | No Connect. Floating pin. | |
| VIN | 5,6 | P | Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and GND with short and wide traces. |
| RT/SYNC | 7 | A | Resistor timing or external clock input. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is now a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to frequency programming by resistor. |
| FB | 8 | A | Feedback input to the regulator. Connect to tap point of the feedback voltage divider. Do not float. Do not ground. |
| PG | 9 | A | Open-drain power-good flag output. Connect to a suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. The flag pulls low when EN = low. Can be left open when not used. |
| BOOT | 10 | P | Bootstrap supply voltage for the internal high-side driver. Connect a high-quality 100nF capacitor from this pin to the SW pin. |
| SW | 11,12 | P | Regulator switch node. Connect to a power inductor. |
| EP | THERMAL PAD | Thermal | Connect to system ground. |
(1) A = Analog, P = Power, G = Ground