ZHCSP51B december   2020  – may 2023 LMR43610 , LMR43620

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable, Start-Up, and Shutdown
      2. 8.3.2  External CLK SYNC (with MODE/SYNC)
        1. 8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 8.3.3  Adjustable Switching Frequency (with RT)
      4. 8.3.4  Power-Good Output Operation
      5. 8.3.5  Internal LDO, VCC, and VOUT/FB Input
      6. 8.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 8.3.7  Output Voltage Selection
      8. 8.3.8  Soft Start and Recovery from Dropout
        1. 8.3.8.1 Recovery from Dropout
      9. 8.3.9  Current Limit and Short Circuit
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 FB for Adjustable Output
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 CFF Selection
          1. 9.2.2.8.1 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Ground and Thermal Considerations
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted. Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VINMIN Input voltage rising threshold for start-up  Before start-up 3.2 3.35 3.5 V
Input voltage falling threshold After operating 2.45 2.7 3 V
ISD(VIN) Shutdown quiescent current at VIN pin EN = 0 V 0.25 1 µA
IBIAS Non-switching input current at VOUT/FB Fixed 5.0-V Vout, VVOUT/FB = 5.25 V 4.2 6.5 µA
IBIAS Non-switching input current at VOUT/FB Fixed 3.3-Vout, VVOUT/FB = 3.47 V 4.2 6.5 µA
IQVIN(nonsw) Non-switching input current; measured at VIN pin (1) Fixed 5.0-V VOUT, VVOUT/FB = 5.25 V 1.6 3 µA
IQVIN(nonsw) Non-switching input current; measured at VIN pin (1) Fixed 3.3-V VOUT, VVOUT/FB = 3.47 V 1.2 2.2 µA
ENABLE (EN PIN)
VEN-WAKE EN wakeup threshold  0.5 0.7 1 V
VEN-VOUT Precision enable rising threshold for VOUT 1.16 1.23 1.3 V
VEN-HYST Enable hysteresis below VEN-VOUT 0.3 0.35 0.4 V
ILKG-EN Enable pin input leakage current VEN = VIN = 13.5 V 10 nA
INTERNAL LDO (VCC PIN)
VCC VCC pin output voltage VFB = 0 V, IVCC = 1 mA 3.1 3.3 3.45 V
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT Output voltage accuracy for fixed VOUT 3.3-V VOUT, VIN = 3.6 V to 36 V, FPWM Mode 3.27 3.3 3.33 V
VOUT Output voltage accuracy for fixed VOUT 5-V VOUT, VIN = 5.5 V to 36 V, FPWM Mode 4.94 5.00 5.06 V
VFB Internal reference voltage accuracy VOUT = 1 V, VIN = 3.0 V to 36 V, FPWM Mode 0.99 1.00 1.01 V
IFB(LKG) FB input current Adjustable configuration, FB = 1 V 10 nA
CURRENT LIMITS
IPEAKMAX High-side peak current limit LMR43610 1.4 1.8 2.1 A
IVALMAX Low-side valley current limit LMR43610 0.85 1.1 1.4 A
IPEAKMIN Minimum peak current limit LMR43610, Auto Mode 0.17 0.27 0.4 A
INEGMIN Low-side valley current negative limit LMR43610, FPWM Mode -1 -0.8 -0.6 A
IPEAKMAX High-side peak current limit LMR43620 2.8 3.4 3.9 A
IVALMAX Low-side valley current limit LMR43620 1.9 2.2 2.53 A
IPEAKMIN Minimum peak current limit LMR43620, Auto Mode 0.37 0.5 0.65 A
INEGMIN Negative current limit LMR43620, FPWM Mode -1 -0.8 -0.6 A
IZC Zero-cross current limit Auto Mode 30 80 135 mA
POWER GOOD (PGOOD PIN)
PGDOV PGOOD upper threshold - rising % of VOUT/FB (Fixed or Adj. output) 104 108 111 %
PGDUV PGOOD upper threshold - falling % of VOUT/FB (Fixed or Adj. output) 89 91 94.2 %
PGDHYST PGOOD recovery hysteresis for OV % of VOUT/FB target regulation voltage 2 2.4 2.8 %
PGOOD recovery hysteresis for UV % of VOUT/FB target regulation voltage 1.1 3.3 5.9 %
VPGD-VAL Minimum VIN for PGOOD function VEN = 0 V, RPGD_PU = 10 kΩ 1.5 V
RPGD PGOOD ON resistance VEN = 3.3 V, 200 µA pull up current  100 Ω
RPGD PGOOD ON resistance VEN = 0 V, 200 µA pull up current 100 Ω
Soft Start
POWER STAGE
VBOOT_UVLO Voltage on BOOT pin compared to SW which will turnoff high-side switch 2.1 V
RDSON-HS High-side MOSFET on-resistance Load = 1 A 132 260 mΩ
RDSON-LS Low-side MOSFET on-resistance Load = 1 A 75 140 mΩ
SOFT START
tSS Time from first SW pulse to VOUT/FB at 90% of set point. 2 3.5 4.6 ms
tHICCUP Time in hiccup before retry soft start 30 50 75 ms
POWER GOOD (PGOOD PIN)
tRESET_FILTER PGOOD deglitch delay at falling edge 25 40 75 µs
tPGOOD_ACT Delay time to PGOOD high signal 1.35 2.5 4 ms
OSCILLATOR (SYNC/MODE PIN)
tPULSE_H High duration needed to be recognized as a pulse 100 ns
tPULSE_L​​​ Low duration needed to be recognized as a pulse 100 ns
tSYNC High/Low level pulse maximum duration to be recognized as a valid clock signal 6 µs
tMODE Time at one level needed to indicate FPWM or Auto Mode 12.5 µs
OSCILLATOR (SYNC/MODE PIN)
FSW(1MHz) Frequency of 1MHz variant in FPWM 0.9 1 1.1 MHz
fSYNC Frequency SYNC range 0.2 2.5 MHz
VMODE_L SYNC/MODE input voltage low level threshold 1 V
VMODE_H SYNC/MODE input voltage high level threshold 1.6 V
OSCILLATOR (RT PIN)
FSW(1MHz) Switching frequency with Internal fixed 1 MHz setting RT pin tie to VCC 0.9 1 1.1 MHz
FSW(2p2MHz) Switching frequency with fixed 2.2 MHz RT pin tied to GND 2.1 2.2 2.3 MHz
FSW(Adj) Accuracy of external frequency, 400 kHz RRT = 39.2 kΩ 0.1% resistor 0.34 0.4 0.46 MHz
SWITCH NODE
tON-MIN Minimum HS switch on-time FPWM mode IOUT = 1 A, 2.2 MHz fixed 65 75 ns
tOFF-MIN Minimum HS switch off-time 60 85 ns
tON-MAX Maximum HS switch on-time HS timeout in dropout 6 9 13 µs
(1) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
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