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SLUSF64A August 2024 – November 2024 LMR51635

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机械数据 (封装 | 引脚)

DDC|6
- MPDS124I

散热焊盘机械数据 (封装 | 引脚)

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8.2.2.5 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. Minimizing the output capacitance to keep cost and size down is generally desirable. The output capacitor or capacitors, C_OUT, must be chosen with care because the choice directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 10.

∆ V_{O U T_E S R} = ∆ i_{L} \times E S R = K_{I N D} {\times I}_{O U T} \times E S R

The other part is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 11.

∆ V_{O U T_C} = \frac{∆ i_{L}}{8 \times f_{S W} \times C_{O U T}} = \frac{K_{I N D} {\times I}_{O U T}}{8 \times f_{S W} \times C_{O U T}}

The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than the sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rates. When a large load step occurs, output capacitors provide the required charge before the inductor current can slew to an appropriate level. The control loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new load level during this time. The output capacitance must be large enough to supply the current difference for eight clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum output capacitance needed for a specified V_OUT overshoot and undershoot.

Equation 12.

C_{O U T} > \frac{1}{2} \times \frac{8 \times (I_{O H} - I_{O L})}{f_{S W} \times ∆ V_{O U T_S H O O T}}

where

K_IND = Ripple ratio of the inductor current (Δi_L / I_OUT)
I_OL = Low level output current during load transient
I_OH = High level output current during load transient
V_{OUT_SHOOT} = Target output voltage overshoot or undershoot

For this design example, the target output ripple is 25mV. Assuming ΔV_{OUT_ESR} = ΔV_{OUT_C} = 25mV, choose K_IND = 0.35. Equation 10 yields ESR no larger than 20mΩ and Equation 11 yields C_OUT no smaller than 15.2µF. For the target overshoot and undershoot limitation of this design, ΔV_{OUT_SHOOT} is 250mV. The C_OUT can be calculated to be no less than 70µF by Equation 12. Three 22µF, 16V ceramic capacitors are used.