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ZHCSCF8E March 2013 – October 2017 LMT84

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DCK|5
- MPDS025I
LP|3
- MSOT002D
LPG|3
- MPBC003B

散热焊盘机械数据 (封装 | 引脚)

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾⁽³⁾

	MIN	MAX	UNIT
Supply voltage	–0.3	6	V
Voltage at output pin	–0.3	(V_DD + 0.5)	V
Output current	–7	7	mA
Input current at any pin⁽²⁾	–5	5	mA
Maximum junction temperature (T_JMAX)		150	°C
Storage temperature T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When the input voltage (V_I) at any pin exceeds power supplies (V_I < GND or V_I > V), the current at that pin should be limited to 5 mA.

(3) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.

7.2 ESD Ratings

			VALUE	UNIT
LMT84LP in TO-92/TO-92S package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽³⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V
LMT84DCK in SC70 package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per JESD22-A114⁽³⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

7.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Specified temperature	T_MIN ≤ T_A ≤ T_MAX		°C
Specified temperature	−50 ≤ T_A ≤ 150		°C
Supply voltage (V_DD)	1.5	5.5	V

7.4 Thermal Information⁽¹⁾

THERMAL METRIC⁽²⁾		LMT84/ LMT84-Q1	LMT84LP	LMT84LPG	UNIT
		DCK (SOT/SC70)	LP/LPM (TO-92)	LPG (TO-92S)
		5 PINS	3 PINS	3 PINS
R_θJA	Junction-to-ambient thermal resistance ⁽³⁾⁽⁴⁾	275	167	130.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	84	90	64.2	°C/W
R_θJB	Junction-to-board thermal resistance	56	146	106.2	°C/W
ψ_JT	Junction-to-top characterization parameter	1.2	35	14.6	°C/W
ψ_JB	Junction-to-board characterization parameter	55	146	106.2	°C/W

(1) For information on self-heating and thermal response time see section Mounting and Thermal Conductivity.

(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

(3) The junction to ambient thermal resistance (R_θJA) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5.

(4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.5 Accuracy Characteristics

These limits do not include DC load regulation. These stated accuracy limits are with reference to the values in Table 3.

PARAMETER	TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
Temperature accuracy ⁽³⁾	70°C to 150°C; V_DD = 1.5 V to 5.5 V	–2.7	±0.6	2.7	°C
	0°C to 70°C; V_DD = 1.5 V to 5.5 V	–2.7	±0.9	2.7	°C
	–50°C to +0°C; V_DD = 1.6 V to 5.5 V	–2.7	±0.9	2.7	°C
	–50°C to +150°C; V_DD = 2.3 V to 5.5 V		±0.4		°C

(1) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

(2) Typicals are at T_J = T_A = 25°C and represent most likely parametric norm.

(3) Accuracy is defined as the error between the measured and reference output voltages, tabulated in Table 3 at the specified conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the specified conditions. Accuracy limits do not include load regulation; they assume no DC load.

7.6 Electrical Characteristics

Unless otherwise noted, these specifications apply for V_DD = +1.5 V to +5.5 V. minimum and maximum limits apply for T_A = T_J = T_MIN to T_MAX; typical values apply for T_A = T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX ⁽¹⁾	UNIT
	Sensor gain			–5.5		mV/°C
	Load regulation ⁽³⁾	Source ≤ 50 μA, (V_DD – V_OUT) ≥ 200 mV	–1	–0.22		mV
	Load regulation ⁽³⁾	Sink ≤ 50 μA, V_OUT ≥ 200 mV		0.26	1	mV
	Line regulation ⁽⁴⁾			200		μV/V
I_S	Supply current	T_A = 30°C to 150°C, (V_DD – V_OUT) ≥ 100 mV		5.4	8.1	μA
I_S	Supply current	T_A = –50°C to 150°C, (V_DD – V_OUT) ≥ 100 mV		5.4	9	μA
C_L	Output load capacitance			1100		pF
	Power-on time ⁽⁵⁾	C_L= 0 pF to 1100 pF		0.7	1.9	ms
	Output drive			±50		µA

(1) Limits are specific to TI's AOQL (Average Outgoing Quality Level).

(2) Typicals are at T_J = T_A = 25°C and represent most likely parametric norm.

(3) Source currents are flowing out of the LMT84-xx. Sink currents are flowing into the LMT84-xx.

(4) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Output Voltage Shift.

(5) Specified by design and characterization.