at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Figure 6-1 IB and IOS vs Temperature
Figure 6-3 Open-Loop Gain vs Temperature
Figure 6-5 Open-Loop Gain vs Output Voltage
Figure 6-7 Output Voltage vs Output Current (Claw)
Figure 6-9 DC PSRR vs Temperature
|
VCM = (V–) – 0.1 V to (V+) – 1.4
V |
|
Figure 6-11 DC CMRR vs Temperature
Figure 6-13 Input Voltage Noise Spectral Density
| VS = 5.5 V,
VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80
kHz |
|
Figure 6-15 THD + N vs Amplitude
Figure 6-17 Quiescent Current vs Temperature
Figure 6-19 Small
Signal Overshoot vs Capacitive Load
Figure 6-21 Phase
Margin vs Capacitive Load
Figure 6-23 Overload Recovery
| G = 1, VIN = 4
VPP, CL = 10 pF |
|
Figure 6-25 Large-Signal Step Response
| G = 1, CL = 100
pF, 2-V step |
Figure 6-27 Large-Signal Settling Time (Positive)
Figure 6-29 Maximum Output Voltage vs Frequency
Figure 6-31 Channel Separation
Figure 6-2 IB and IOS vs Common-Mode Voltage
Figure 6-4 Open-Loop Gain and Phase vs Frequency
Figure 6-6 Closed-Loop Gain vs Frequency
Figure 6-8 PSRR vs Frequency
Figure 6-10 CMRR vs Frequency
Figure 6-12 0.1 Hz to 10 Hz Integrated Voltage Noise
| VS = 5.5 V,
VCM = 2.5 V, G = 1, BW = 80 kHz,
VOUT = 0.5 VRMS |
Figure 6-14 THD + N vs Frequency
Figure 6-16 Quiescent Current vs Supply Voltage
Figure 6-18 Open-Loop Output Impedance vs Frequency
Figure 6-20 Small
Signal Overshoot vs Capacitive Load
Figure 6-22 No
Phase Reversal
| G = 1, VIN = 100
mVPP, CL = 10 pF |
|
Figure 6-24 Small-Signal Step Response
| G = 1, CL = 100
pF, 2-V step |
|
Figure 6-26 Large-Signal Settling Time (Negative)
Figure 6-28 Short-Circuit Current vs Temperature
Figure 6-30 Electromagnetic Interference Rejection Ratio
Referred to Non-inverting Input (EMIRR+) vs Frequency