8.1.1 Basic Comparator

The comparator compares the input voltage (V_IN) at the non-inverting pin to the reference voltage (V_REF) at the inverting pin. If V_IN is less than V_REF, the output voltage (V_O) is at the saturation voltage. On the other hand, if V_IN is greater than V_REF, the output voltage (V_O) is at V_CC.

Figure 10. Basic Comparator

8.1.2 Comparator With Hysteresis

The basic comparator configuration may oscillate or produce a noisy output if the applied differential input voltage is near the comparator's offset voltage. This usually happens when the input signal is moving very slowly across the switching threshold of the comparator. This problem can be prevented by the addition of hysteresis or positive feedback.

8.1.2.1 Inverting Comparator With Hysteresis

The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply voltage V_CC of the comparator. When V_in at the inverting input is less than V_a, the voltage at the non-inverting node of the comparator (V_in < V_a), the output voltage is high (for simplicity assume V_O switches as high as V_CC). The three network resistors can be represented as R₁//R₃ in series with R₂. The lower input trip voltage V_a1 is defined as:

Equation 1.

When V_in is greater than V_a (V_in > V_a), the output voltage is low very close to ground. In this case the three network resistors can be presented as R₂//R₃ in series with R₁. The upper trip voltage V_a2 is defined as:

Equation 2.

The total hysteresis provided by the network is defined as:

Equation 3. ΔV_a = V_a1 - V_a2

To assure that the comparator will always switch fully to V_CC and not be pulled down by the load the resistors values should be chosen as follow:

Equation 4. R_PULL-UP << R_LOAD

Equation 5. and R₁ > R_PULL-UP.

Figure 11. Inverting Comparator With Hysteresis

8.1.2.1.1 Non-inverting Comparator With Hysteresis

Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (V_ref) at the inverting input. When V_in is low, the output is also low. For the output to switch from low to high, V_in must rise up to V_in1 where V_in1 is calculated by:

Equation 6.

When V_in is high, the output is also high. To make the comparator switch back to its low state, V_in must equal V_ref before V_A will again equal V_ref. V_in can be calculated by:

Equation 7.

The hysteresis of this circuit is the difference between V_in1 and V_in2.

Equation 8. ΔV_in = V_CCR₁/R₂

Figure 12. Noninverting Comparator With Hystersis

Figure 13. Hysteresis Threshold Points

8.1.3 ORing the Output

By the inherit nature of an open-collector comparator, the outputs of several comparators can be tied together with a shared pull-up resistor to V_CC. If one or more of the comparators outputs goes low, the output V_O will go low.

Figure 14. ORing the Outputs

8.1.4 Driving CMOS and TTL

The output of the comparator is capable of driving CMOS and TTL Logic circuits. The pull-up resistor may be pulled-up to any voltage equal to, or less than the supply voltage on V+. However, it must not be pulled-up to a voltage higher than V+.

Figure 15. Driving CMOS

Figure 16. Driving TTL

8.1.5 AND Gates

The comparator can be used as three input AND gate. The operation of the gate is as follows:

The resistor divider at the inverting input establishes a reference voltage at that node. The non-inverting input is the sum of the voltages at the inputs divided by the voltage dividers. The output will go high only when all three inputs are high, casing the voltage at the non-inverting input to go above that at inverting input. The circuit values shown work for a 0 equal to ground and a 1 equal to 5 V.

The resistor values can be altered if different logic levels are desired. If more inputs are required, diodes are recommended to improve the voltage margin when all but one of the inputs are high.

Figure 17. AND Gate

8.1.6 OR Gates

A three input OR gate is achieved from the basic AND gate simply by increasing the resistor value connected from the inverting input to V_cc, thereby reducing the reference voltage.

A logic 1 at any of the inputs will produce a logic 1 at the output.

Figure 18. OR Gate

8.1.7 Large Fan-In Gate

Extra logic inputs may be added by ORing the input with multiple diodes.

Figure 19. Large Fan-In and Gate

8.2.1 Squarewave Oscillator

Figure 20. Squarewave Oscillator

8.2.1.2 Detailed Design Procedure

Figure 21. Squarewave Oscillator Timing Thresholds

To analyze the circuit, assume that the output is initially high. For this to be true, the voltage at the inverting input V_c has to be less than the voltage at the non-inverting input V_a. For V_c to be low, the capacitor C₁ has to be discharged and will charge up through the negative feedback resistor R₄. When it has charged up to value equal to the voltage at the positive input V_a1, the comparator output will switch.

V_a1 will be given by:

Equation 9.

If:

Equation 10. R₁ = R₂ = R₃

Then:

Equation 11. V_a1 = 2V_CC/3

When the output switches to ground, the value of V_a is reduced by the hysteresis network to a value given by:

Equation 12. V_a2 = V_CC/3

Capacitor C₁ must now discharge through R₄ towards ground. The output will return to its high state when the voltage across the capacitor has discharged to a value equal to V_a2.

For the circuit shown, the period for one cycle of oscillation will be twice the time it takes for a single RC circuit to charge up to one half of its final value. The time to charge the capacitor can be calculated from:

Equation 13.

Where V_max is the max applied potential across the capacitor = (2V_CC/3)

and V_C = Vmax/2 = V_CC/3

One period will be given by:

Equation 14. 1/freq = 2t

or calculating the exponential gives:

Equation 15. 1/freq = 2(0.694) R₄ C₁

Resistors R₃ and R₄ must be at least two times larger than R₅ to ensure that V_O will go all the way up to V_CC in the high state. The frequency stability of this circuit should strictly be a function of the external components.

8.2.1.3 Application Curve

Figure 22. Waveforms for Circuit in Typical Applications

8.2.2 Crystal Controlled Oscillator

Figure 23. Crystal Controlled Oscillator

A simple yet very stable oscillator that generates a clock for slower digital systems can be obtained by using a resonator as the feedback element. It is similar to the squarewave oscillator, except that the positive feedback is obtained through a quartz crystal. The circuit oscillates when the transmission through the crystal is at a maximum, so the crystal in its series-resonant mode.

The value of R₁ and R₂ are equal so that the comparator will switch symmetrically about +V_CC/2. The RC constant of R₃ and C₁ is set to be several times greater than the period of the oscillating frequency, insuring a 50% duty cycle by maintaining a DC voltage at the inverting input equal to the absolute average of the output waveform.

When specifying the crystal, be sure to order series resonant with the desired temperature coefficient.

8.2.3 Pulse Generator With Variable Duty Cycle

Figure 24. Pulse Generator With Variable Duty Cycle

The pulse generator with variable duty cycle is just a minor modification of the basic square wave generator. Providing a separate charge and discharge path for capacitor C₁generates a variable duty cycle. One path, through R₂ and D₂ will charge the capacitor and set the pulse width (t₁). The other path, R₁ and D₁ will discharge the capacitor and set the time between pulses (t₂).

By varying resistor R₁, the time between pulses of the generator can be changed without changing the pulse width. Similarly, by varying R₂, the pulse width will be altered without affecting the time between pulses. Both controls will change the frequency of the generator. The pulse width and time between pulses can be found from:

Equation 16.

Solving these equations for t₁ and t₂

These terms will have a slight error due to the fact that V_max is not exactly equal to 2/3 V_CC but is actually reduced by the diode drop to:

Equation 19.

Equation 20.

Equation 21.

8.2.4 Positive Peak Detector

Figure 25. Positive Peak Detector

Positive peak detector is basically the comparator operated as a unit gain follower with a large holding capacitor from the output to ground. Additional transistor is added to the output to provide a low impedance current source. When the output of the comparator goes high, current is passed through the transistor to charge up the capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the output. The decay time can be altered simply by changing the 1-MΩ resistor. The output should be used through a high impedance follower to a avoid loading the output of the peak detector.

8.2.5 Negative Peak Detector

Figure 26. Negative Peak Detector

For the negative detector, the output transistor of the comparator acts as a low impedance current sink. The only discharge path will be the 1-MΩ resistor and any load impedance used. Decay time is changed by varying the 1-MΩ resistor.