8.2.1 Design Requirements

The lower input bias current of the LMV601 results in a very high input impedance. The output impedance when the device is in shutdown mode is quite high. These high impedances, and the ability of the shutdown pin to be derived from a separate power source, make LMV601 a good choice for sample and hold circuits. The sample clock must be connected to the shutdown pin of the amplifier to rapidly turn the device on or off.

8.2.2 Detailed Design Procedure

Figure 46 shows the schematic of a simple sample-and-hold circuit. When the sample clock is high, the first amplifier is in normal operation mode and the second amplifier acts as a buffer. The capacitor, which appears as a load on the first amplifier, is charging at this time. The voltage across the capacitor is that of the noninverting input of the first amplifier because it is connected as a voltage-follower. When the sample clock is low, the first amplifier is shut off, bringing the output impedance to a high value. The high impedance of this output, along with the very high impedance on the input of the second amplifier, prevents the capacitor from discharging. There is very little voltage droop while the first amplifier is in shutdown mode. The second amplifier, which is still in normal operation mode and is connected as a voltage-follower, also provides the voltage sampled on the capacitor at its output.

8.2.3 Application Curve

Figure 47. Sample-and-Hold Circuit Results