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SNAS187D February 2003 – January 2016 LMX2430 , LMX2433 , LMX2434

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

NPE|20
- MPLG058

散热焊盘机械数据 (封装 | 引脚)

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7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

		MIN	MAX	UNIT
	Power supply voltage V_CC to GND	−0.3	3.25	V
V_I	Voltage on any pin to GND V_I must be < +3.25 V	−0.3	V_CC + 0.3	V
T_L	Lead temperature (solder 4 seconds)		260	°C
T_stg	Storage temperature	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This device is a high-performance RF integrated circuit with an ESD rating < 2000 V and is ESD-sensitive. Handling and assembly of this device must be done at ESD-protected work stations.

(3) GND = 0 V.

(4) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.

7.2 Recommended Operating Conditions

	MIN	MAX	UNIT
Power supply voltage Vcc to GND	2.25	2.75	V
Operating temperature, T_A	−40	85	°C

7.3 Thermal Information

THERMAL METRIC⁽¹⁾		LMX243x		UNIT
		NPE (ULGA)	PW (TSSOP)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	80.9	111.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	22.5	44.9	°C/W
R_θJB	Junction-to-board thermal resistance	40	63.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	6.1	°C/W
ψ_JB	Junction-to-board characterization parameter	40	62.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Electrical Characteristics

V_CC = EN = 2.5 V, −40°C ≤ T_A ≤ +85°C, unless otherwise specified

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_CC PARAMETERS
I_CC_RF	Power supply current, RF synthesizer	LMX2430	CLK, DATA and LE = 0 V OSCin = GND RF_PD Bit = 0 IF_PD Bit = 1 RF_P Bit = 0		2.8	3.6	mA
		LMX2433			3.2	4.4	mA
		LMX2434			4.6	6.2	mA
I_CC_IF	Power supply current, IF synthesizer	LMX2430	CLK, DATA and LE = 0 V OSCin = GND RF_PD Bit = 1 IF_PD Bit = 0 IF_P Bit = 0		1.4	2	mA
		LMX2433			2	2.8	mA
		LMX2434			2.4	3.5	mA
I_CC_PD	Power-down current		EN, ENosc, CLK, DATA and LE = 0 V			10	μA
RF SYNTHESIZER PARAMETERS
f_FinRF	RF operating frequency	LMX2430	RF_P Bit = 0	250		2500	MHz
		LMX2430	RF_P Bit = 1	250		3000	MHz
		LMX2433	RF_P Bit = 0	500		3000	MHz
		LMX2433	RF_P Bit = 1	500		3600	MHz
		LMX2434	RF_P Bit = 0 or 1	1000		5000	MHz
N_RF	N divider range		P = 8 / 9⁽¹⁾	24		262,151
			P = 16 / 17⁽¹⁾	48		524,287
			P = 32 / 33⁽¹⁾	96		524,287
R_RF	RF R divider range			3		32,767
f_COMPRF	RF phase detector frequency					10	MHz
p_FinRF	RF input sensitivity		LMX2430 / 33 2.25 V ≤ V_CC ≤ 2.75 V⁽²⁾	−15		0	dBm
p_FinRF	RF input sensitivity		LMX2434 2.35 V ≤ V_CC ≤ 2.75 V⁽²⁾	−12		0	dBm
I_CPoutRF Source	RF charge-pump output source current		V_CPoutRF = V_CC / 2 RF_CPG Bit = 0⁽³⁾		–1		mA
I_CPoutRF Source	RF charge-pump output source current		V_CPoutRF = V_CC / 2 RF_CPG Bit = 1⁽³⁾		–4		mA
I_CPoutRF Sink	RF charge-pump output sink current		V_CPoutRF = V_CC / 2 RF_CPG Bit = 0⁽³⁾		1		mA
I_CPoutRF Sink	RF charge-pump output sink current		V_CPoutRF = V_CC / 2 RF_CPG Bit = 1⁽³⁾		4		mA
I_CPoutRF TRI	RF charge-pump output tri-state current		0.5 V ≤ V_CPoutRF ≤ V_CC – 0.5 V⁽³⁾	–2.5		2.5	nA
I_CPoutRF %MIS	RF charge-pump output sink current vs charge-pump output source current mismatch		V_CPoutRF = V_CC / 2⁽⁴⁾		3%	10%
I_CPoutRF %V_CPoutRF	RF charge-pump output current magnitude variation vs charge-pump output voltage		0.5 V ≤ V_CPoutRF ≤ V_CC – 0.5 V⁽⁴⁾		5%	15%
I_CPoutRF %T_A	RF charge-pump output current magnitude variation vs temperature		V_CPoutRF = V_CC / 2⁽⁴⁾		2%
IF SYNTHESIZER PARAMETERS
f_FinIF	IF operating frequency	LMX2430	IF_P Bit = 0 or 1	100		800	MHz
		LMX2433	IF_P Bit = 0 or 1	250		1700	MHz
		LMX2434	IF_P Bit = 0 or 1	500		2500	MHz
N_IF	IF N divider range		P = 8/9⁽¹⁾	24		131,079
N_IF	IF N divider range		P = 16/17⁽¹⁾	48		262,143
R_IF	IF R divider range			3		32,767
f_COMPIF	IF phase detector frequency					10	MHz
p_FinIF	IF input sensitivity		2.25 V ≤ V_CC ≤ 2.75 V⁽²⁾	–15		0	dBm
I_CPoutIF Source	IF charge-pump output source current		V_CPoutIF = V_CC/2 IF_CPG Bit = 0⁽³⁾		–1		mA
I_CPoutIF Source	IF charge-pump output source current		V_CPoutIF = V_CC/2 IF_CPG Bit = 1⁽³⁾		–4		mA
I_CPoutIF Sink	IF charge-pump output sink current		V_CPoutIF = V_CC/2 IF_CPG Bit = 0⁽³⁾		1		mA
I_CPoutIF Sink	IF charge-pump output sink current		V_CPoutIF = V_CC/2 IF_CPG Bit = 1⁽³⁾		4		mA
I_CPoutIF TRI	IF charge-pump output tri-state current		0.5 V ≤ V_CPoutIF ≤ V_CC – 0.5 V⁽³⁾	–2.5		2.5	nA
I_CPoutIF %MIS	IF charge-pump output sink current vs charge-pump output source current mismatch		V_CPoutIF = V_CC/2⁽⁴⁾		3%	10%
I_CPoutIF %V_CPoutIF	IF charge-pump output current magnitude variation vs charge-pump output voltage		0.5 V ≤ V_CPoutIF ≤ V_CC – 0.5 V⁽⁴⁾		5%	15%
I_CPoutIF %T_A	IF charge-pump output current magnitude variation vs temperature		V_CPoutIF = V_CC/2⁽⁴⁾		2%
OSCILLATOR PARAMETERS
f_OSCin	Oscillator operating frequency			1		256	MHz
v_OSCin	Oscillator sensitivity		See ⁽⁵⁾	0.5		V_CC	V_PP
I_OSCin	Oscillator input current		V_OSCin = V_CC			100	µA
I_OSCin	Oscillator input current		V_OSCin = 0 V	–100			µA
DIGITAL INTERFACE (DATA, CLK, LE, EN, ENosc, Ftest/LD, FLoutRF, OSCout/ FLoutIF)
V_IH	High-level input voltage			1.6			V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current		V_IH = V_CC			1	μA
I_IL	Low-level input current		V_IL = 0 V	−1			μA
V_OH	High-level output voltage		I_OH = −500 μA	V_CC − 0.4			V
V_OL	Low-level output voltage		I_OL = 500 μA			0.4	V
PHASE NOISE CHARACTERISTICS
L_NRF(f)	RF synthesizer normalized phase noise contribution⁽⁷⁾		TCXO Reference Source RF_CPG Bit = 1 IF_PD Bit = 1		–219		dBc/ Hz
L_NIF(f)	IF synthesizer normalized phase noise contribution⁽⁷⁾		TCXO Reference Source IF_CPG Bit = 1 RF_PD Bit = 1		–214		dBc/ Hz
L_RF(f)	RF synthesizer single-side band phase noise measured	LMX2430	f_FinRF = 2750 MHz f = 10-kHz offset f_COMPRF = 1 MHz Loop Bandwidth = 100 kHz N_RF = 2750 f_OSCin = 10 MHz v_OSCin = 1 V_PP RF_CPG Bit = 1 IF_PD Bit = 1 T_A = 25^oC⁽⁸⁾		–90.3		dBc/ Hz
		LMX2433	f_FinRF = 3200 MHz f = 10-kHz offset f_COMPRF = 1 MHz Loop Bandwidth = 100 kHz N_RF = 3200 f_OSCin = 10 MHz v_OSCin = 1 V_PP RF_CPG Bit = 1 IF_PD Bit = 1 T_A = 25°C⁽⁸⁾		–88.9		dBc/ Hz
		LMX2434	f_FinRF = 4700 MHz f = 10-kHz offset f_COMPRF = 1 MHz Loop Bandwidth = 100 kHz N_RF = 4700 f_OSCin = 10 MHz v_OSCin = 1 V_PP RF_CPG Bit = 1 IF_PD Bit = 1 T_A = 25°C⁽⁸⁾		–85.6		dBc/ Hz

(1) Some of the values in this range are illegal divide ratios (B < A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N ≥ P * (P−1), where P is the value of the prescaler selected.

(2) Refer to LMX243x FinRF Sensitivity Test Set-Up.

(3) Refer to LMX243x Charge Pump Test Set-Up.

(4) Refer to Charge Pump Current Specification Definitions for details on how these measurements are made.

(5) Refer to LMX243x OSCin Sensitivity Test Set-Up.

(6) Refer to LMX243x Serial Data Input Timing figure.

(7) Normalized Phase Noise Contribution is defined as L_N(f) = L(f) − 20 log (N) − 10 log (f_COMP), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the loop bandwidth of the PLL, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and f_COMP is the RF/IF phase and frequency detector comparison frequency.

(8) The synthesizer phase noise is measured with the LMX2430PW/LMX2430NPE evaluation boards and the HP8566B Spectrum Analyzer.

7.5 Timing Requirements

See ⁽⁶⁾

		MIN	UNIT
MICROWIRE INTERFACE
t_CS	DATA to CLK set-up time	50	ns
t_CH	DATA to CLK hold time	10	ns
t_CWH	CLK pulse width HIGH	50	ns
t_CWL	CLK pulse width LOW	50	ns
t_ES	CLK to LE set-up time	50	ns
t_EW	LE pulse width	50	ns