米6体育平台手机版

ZHCSFL5A October 2016 – January 2017 LMX2491

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RTW|24
- MPQF167C

散热焊盘机械数据 (封装 | 引脚)

RTW|24
- QFND450A

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CP	Supply voltage for charge pump	V_CC	5.5	V
V_CC	Supply voltage	–0.3	3.6	V
V_IN	I/O input voltage	–0.3	V_CC + 0.3	V
T_Solder	Lead temperature (solder 4 seconds)		260	°C
T_Junction	Junction temperature		150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

applicable before the DMD is installed in the final product

			MIN	MAX	UNIT
T_stg	DMD storage temperature		–65	150	°C
T_DP	Storage dew point			3	°C

6.3 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	3.15	3.3	3.45	V
V_CP	Charge pump supply voltage	V_CC		5.25	V
T_A	Ambient temperature	–40		85	°C
T_J	Junction temperature	–40		125	°C

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		LMX2491	UNIT
		RTW (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	39.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.1	°C/W
ψ_JB	Junction-to-board characterization parameter	20	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, V_CC ≤ V_CP ≤ 5.25 V, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_CP = 3.3 V, 25 °C.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_CC	Current consumption	All Vcc pins	f_PD = 10 MHz		45		mA
			f_PD = 100 MHz		50
			f_PD = 200 MHz		55
		Vcp pin	K_PD = 0.1 mA		2
			K_PD = 1.6 mA		10
			K_PD = 3.1 mA		19
I_CCPD	Power down current	POWERDOWN			3
f_OSCin	Frequency for OSCin terminal	OSC_DIFFR = 0, doubler disabled		10		600	MHz
		OSC_DIFFR = 0, doubler enabled		10		300
		OSC_DIFFR = 1, doubler disabled		10		1200
		OSC_DIFFR = 1, doubler enabled		10		600
V_OSCin	Voltage for OSCin pin⁽¹⁾			0.5		V_CC – 0.5	V_PP
f_Fin	Frequency for Fin pin			500		6400	MHz
P_Fin	Power for Fin pin	Single-ended operation		–5		5	dBm
f_PD	Phase detector frequency					200	MHz
PN1Hz	PLL figure of merit⁽²⁾				–227		dBc/Hz
PN10kHz	Normalized PLL 1/f noise⁽²⁾	Normalized to 10-kHz offset for a 1-GHz carrier.			–120		dBc/Hz
I_CPoutTRI	Charge pump leakage tri-state leakage					10	nA
I_CPoutMM	Charge pump mismatch⁽³⁾	V_CPout = V_CP / 2			5%
I_CPout	Charge pump current	V_CPout = V_CP / 2	CPG = 1X		0.1		mA
			…
			CPG = 31X		3.1
LOGIC OUTPUT TERMINALS (MUXout, TRIG1, TRIG2, MOD)
V_OH	Output high voltage			0.8 × V_CC	V_CC		V
V_OL	Output low voltage				0	0.2 × V_CC	V
LOGIC INPUT TERMINALS (CE, CLK, DATA, LE, MUXout, TRIG1, TRIG2, MOD)
V_IH	Input high voltage			1.4		V_CC	V
V_IL	Input low voltage			0		0.6	V
I_IH	Input leakage current			–5	1	5	µA
t_CELOW	Chip enable low time			5			µs
t_CEHIGH	Chip enable high time			5			µs

(1) For optimal phase noise performance, higher input voltage and a slew rate of at least 3 V/ns is recommended

(2) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 × log( 10^{PLL_Flat / 10} + 10^{PLL_Flicker(Offset) / 10})
PLL_Flat = PN1Hz + 20 × log(N) + 10 × log(f_PD / 1 Hz)
PLL_Flicker = PN10kHz - 10 × log(Offset / 10 kHz) + 20 × log(f_VCO / 1 GHz)

(3) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.

6.7 Timing Requirements, Programming Interface (CLK, DATA, LE)

		MIN	UNIT
t_CE	Clock to LE low time	10	ns
t_CS	Data to clock setup time	4	ns
t_CH	Data to clock hold time	4	ns
t_CWH	Clock pulse width high	10	ns
t_CWL	Clock pulse width low	10	ns
t_CES	Enable to clock setup time	10	ns
t_EWH	Enable pulse width high	10	ns

Figure 1. Serial Data Input Timing

There are several other considerations for programming:

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter.
If no LE signal is given after the last data bit and the clock is kept toggling, then these bits are read into the next lower register. This eliminates the need to send the address each time.
A slew rate of at least 30 V/µs is recommended for the CLK, DATA, and LE signals
Timing specs also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals.