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SNAS624B March 2014 – May 2015 LMX2492 , LMX2492-Q1

PRODUCTION DATA.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Vcp	Supply voltage for charge pump	Vcc	5.5	V
CPout	Charge pump output pin	-0.3	Vcp	V
Vcc	All Vcc pins	-0.3	3.6	V
Others	All other I/O pins	-0.3	Vcc + 0.3	V
T_Solder	Lead temperature (solder 4 seconds)		260	°C
T_Junction	Junction temperature		150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Storage Conditions

applicable before the DMD is installed in the final product

		MIN	MAX	UNIT
T_stg	DMD storage temperature	-65	150	°C
MSL	Moisture sensitivity level		3	n/a

7.3 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	PARAMETER	DEVICE	MIN	NOM	MAX	UNIT
Vcc	PLL supply voltage		3.15	3.3	3.45	V
Vcp	Charge pump supply voltage		Vcc		5.25	V
T_A	Ambient temperature	LMX2492	-40		85	°C
T_A	Ambient temperature	LMX2492-Q1	-40		125	°C
T_J	Junction temperature	LMX2492	-40		125	°C
T_J	Junction temperature	LMX2492-Q1	-40		135	°C

7.5 Thermal Information

	THERMAL METRIC⁽¹⁾	LMX2492 RTW (WQFN ) 24 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	39.4	°C/W
R_θJC	Junction-to-case thermal resistance	7.1
ψ_JB	Junction-to-board characterization parameter	20

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C.
-40°C ≤ T_A ≤ 85 °C for the LMX2492 and -40°C ≤ T_A ≤ 125 °C for the LMX2492-Q1 ; except as specified.)

	PARAMETER	CONDITIONS		MIN	TYP	MAX	UNIT
Icc	Current Consumption	All Vcc Pins	Fpd = 10 MHz		45		mA
			Fpd = 100 MHz		50
			Fpd = 200 MHz		55
		Vcp Pin	Kpd = 0.1 mA		2
			Kpd = 1.6 mA		10
			Kpd = 3.1 mA		19
IccPD	Current	POWERDOWN			3
f_OSCin	Frequency for OSCin terminal	OSC_DIFFR=0, Doubler Disabled		10		600	MHz
		OSC_DIFFR=0, Doubler Enabled		10		300
		OSC_DIFFR=1, Doubler Disabled		10		1200
		OSC_DIFFR=1, Doubler Enabled		10		600
v_OSCin	Voltage for OSCin Pin⁽¹⁾	LMX2492-Q1 Version Only Single Ended XO 30 MHz ≤ f_OSCin ≤ 100 MHz		0.24		Vcc-0.5	Vpp
v_OSCin	Voltage for OSCin Pin⁽¹⁾	All Other Cases		0.5		Vcc-0.5	Vpp
f_Fin	Frequency for FinPin⁽⁴⁾			500		14000	MHz
p_Fin	Power for Fin Pin	Single-Ended Operation		-5		5	dBm
f_PD	Phase Detector Frequency					200	MHz
PN1Hz	PLL Figure of Merit⁽²⁾				-227		dBc/Hz
PN10kHz	Normalized PLL 1/f Noise⁽²⁾	Normalized to 10 kHz offset for a 1 GHz carrier.			-120		dBc/Hz
I_CPoutTRI	Charge Pump Leakage Tri-state Leakage					10	nA
I_CPoutMM	Charge Pump Mismatch⁽³⁾	V_CPout = Vcp / 2			5 %
I_CPout	Charge Pump Current	V_CPout = Vcp / 2	CPG=1X		0.1		mA
			…
			CPG=31X		3.1
LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD)
V_OH	Output High Voltage			0.8 x Vcc	Vcc		V
V_OL	Output Low Voltage				0	0.2 x Vcc	V
LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD)
V_IH	Input High Voltage			1.4		Vcc	V
V_IL	Input Low Voltage			0		0.6	V
I_IH	Input Leakage			-5	1	5	uA
T_CELOW	Chip enable Low Time			5			us
T_CEHIGH	Chip enable High Time			5			us

(1) For optimal phase noise performance, a slew rate of at least 3 V/ns is recommended

(2) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10×log( 10^PLL_Flat/10 + 10^{PLL_Flicker(Offset)/10})
PLL_Flat = PN1Hz + 20×log(N) + 10×log(Fpd/1Hz)
PLL_Flicker = PN10kHz - 10×log(Offset/10kHz) + 20×log(Fvco/1GHz)

(3) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.

(4) Tested to 13.5 GHz, Guaranteed to 14 GHz by characterization

7.7 Timing Requirements, Programming Interface (CLK, DATA, LE)

		MIN	UNIT
T_CE	Clock To LE Low Time	10	ns
T_CS	Data to Clock Setup Time	4	ns
T_CH	Data to Clock Hold Time	4	ns
T_CWH	Clock Pulse Width High	10	ns
T_CWL	Clock Pulse Width Low	10	ns
T_CES	Enable to Clock Setup Time	10	ns
T_EWH	Enable Pulse Width High	10	ns

Figure 1. Serial Data Input Timing

There are several other considerations for programming:

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter.
If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into the next lower register. This eliminates the need to send the address each time.
A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals
Timing specifications also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals.

7.8 Typical Characteristics

LMX2492 LMX2492-Q1 tc03_cpout3V_snas624.png

For a charge pump supply of 3.3 V, optimal performance is for a typical charge pump output voltage between 0.5 and 2.8 volts.

Figure 2. Charge Pump Current for Vcp = 3.3 V

LMX2492 LMX2492-Q1 tc04_cpout5V_snas624.png

For a charge pump supply voltage of 5 volts or higher, optimal performance is typically for a charge pump output voltage between 0.5 and 4.5 volts.

Figure 3. Charge Pump Current for Vcp = 5.5 V

LMX2492 LMX2492-Q1 tc02_sensitivity_snas624.png

Typical value of lowest power level as a function of frequency. Design to electrical specifications for input sensitivity, not typical performance graphs.

Figure 4. Fin Input Sensitivity

LMX2492 LMX2492-Q1 tc01_pnoise_snas624.png

This plot is for a phase detector of 100 MHz, 2 MHz loop bandwidth, and VCO at 9600 MHz. However, the plot shown is the divide by 2 port at 4800 MHz. The input was a 100 MHz Wenzel Oscillator. The model shows this phase noise has a figure of merit of -227 dBc/Hz and a normalized 1/f noise of -120.5 dBc/Hz. The charge pump supply was 5 V and the charge pump output voltage was 1.34 V.

Figure 5. LMX2492/92-Q1 Phase Noise for Fpd =100 MHz, Fvco = 9600 MHz/2