There are several other considerations for programming:

• A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital control signals such as FSK_D[0:2] and FSK_DV signals.
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the 24^th CLK, the data is transferred from the data field to the selected register bank.
• The LE pin may be held high after programming, causing the LMX2571-EP to ignore clock pulses.
• When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.
• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming.

Figure 6-1 MICROWIRE Timing Diagram