8.2.2 Detailed Design Procedure

First, determine all the elementary blocks of a synthesizer.

Figure 169. Application Example Frequency Plan

Then, program these registers to make LMX2572LP locks to the target output frequency:

• OSC_2X = 0
• PLL_R_PRE = 1
• MULT = 1
• PLL_R = 1
• PLL_N[18:16] = 0; PLL_N[15:0] = 39
• PLL_NUM[31:16] = 24; PLL_NUM[15:0] = 27136
• PLL_DEN[31:16] = 122; PLL_DEN[15:0] = 4680
• CHDIV = 8

Then program these registers to enable FSK SPI FAST mode:

• FSK_MODE_SEL = 3
• FSK_DEV_SCALE = 1
• FSK_EN = 1

A Mathlab script is then developed to generate the necessary codes that will be used to continuously bit-stream the LMX2572LP. These codes are uploaded to the data generator DG2020, which will generate the SPI data to modulate the LMX2572LP.

Figure 170. Application Example Test Setup