7.3.4 PLL N Divider and Fractional Circuitry

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to (2³² – 1). The integer portion of N (PLL_N) is the whole part of the N divider value, and the fractional portion, N_frac = PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM and PLL_DEN are software programmable. The higher the denominator, the finer the resolution step of the output. For example, even when using f_PD = 200 MHz, the output can increment in steps of 200 MHz / (2³² – 1) = 0.0466 Hz. Equation 2 shows the relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is an extra divider that is not shown in Equation 2.

The multi-stage noise-shaping (MASH) sigma-delta modulator that controls the fractional division is also programmable from integer mode to fourth order. All of these settings work for integer channel where PLL_NUM = 0. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

The N divider has minimum value restrictions based on the modulator order. Furthermore, the PFD_DLY_SEL bit must be programmed in accordance to Table 3.