7.5 Programming

The LMX2572LP is programmed using several 24-bit shift registers. The shift register consists of a data field, an address field, and a R/W bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The following seven bits, ADDR[6:0], form the address field which is used to decode the internal register address. The remaining 16 bits form the data field DATA[15:0]. Serial data is shifted MSB first into the shift register. See Figure 1 for timing diagram details.

To write registers:

• The R/W bit must be set to 0.
• The data on SDI pin is clocked into the shift register upon the rising edge of the clocks on SCK pin. On the rising edge of the 24^th clock cycle, the data is transferred from the data field into the selected register bank.
• The CSB pin may be held high after programming, which causes the LMX2572LP to ignore clock pulses.
• If the SCK and SDI lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared between devices, the phase noise may be degraded during the time of this programming.

To read back registers:

• The R/W bit must be set to 1.
• The data field contents on the SDI line are ignored.
• The read back data on MUXout pin is clocked out starting from the falling edge of the 8^th clock cycle.