7.5.3 Double Buffering
Some register fields support double buffering. That is, the change to these fields would not be effective immediately. To latch the new values into the device requires programming R0 again with FCAL_EN = 1. The following register fields support double buffering, see Table 69 for details.
- MASH order (MASH_ORDER)
- Fractional numerator (PLL_NUM)
- N divider (PLL_N)
- Doubler (OSC_2X); Pre-R divider (PLL_R_PRE); Multiplier (MULT); Post-R divider (PLL_R)
For example,
- Program PLL_R and PLL_N to new values. If double buffering for these fields is enabled, the PLL will remain unchanged.
- Program R0 with FCAL_EN = 1. The PLL will calibrate and lock using the new PLL_R and PLL_N values.