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ZHCSEK3G December 2015 – August 2022 LMX2592

PRODUCTION DATA

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请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RHA|40

散热焊盘机械数据 (封装 | 引脚)

RHA|40
- QFND114P

订购信息

6.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, –40°C ≤ T_A ≤ 85°C.
Typical values are at V_CC = 3.3 V, 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
V_CC	Supply voltage				3.3		V
I_CC	Supply current	Single 6-GHz, 0-dBm output⁽¹⁾			250		mA
I_PD	Powerdown current				3.7		mA
OUTPUT CHARACTERISTICS
F_out	Output frequency			20		9800	MHz
P_out	Typical high output power	Output = 3 GHz, 50-Ω pullup, single-ended⁽²⁾			8		dBm
Tcal	VCO calibration time	Reference input = 100 MHz, 7-GHz desired output⁽⁸⁾			590	800	µs
INPUT SIGNAL PATH
REFin	Reference input frequency			5		1400	MHz
REFv	Reference input voltage	AC-coupled, differential⁽³⁾		0.2		2	Vppd
MULin	Input signal path multiplier input frequency			40		70	MHz
MULout	Input signal path multiplier output frequency			180		250	MHz
PHASE DETECTOR AND CHARGE PUMP
PDF	Phase detector frequency			5		200	MHz
PDF	Phase detector frequency	Extended range mode⁽⁴⁾		0.25		400	MHz
CPI	Charge pump current	Programmable		0		12	mA
PLL PHASE NOISE
_{PLL_flicker_Norm}	Normalized PLL Flicker Noise⁽⁵⁾				–126		dBc/Hz
_{PLL_FOM}	Normalized PLL Noise Floor (PLL Figure of Merit)⁽⁵⁾				–231		dBc/Hz
VCO
\|ΔT_CL\|	Allowable temperature drift⁽⁶⁾	VCO not being recalibrated				125	°C
PN_{open loop}	Output = 3 GHz	100 kHz			–118.8		dBc/Hz
		1 MHz			–140.3
		10 MHz			–155.1
		100 MHz			–156.3
	Output = 6 GHz	100 kHz			–112.6
		1 MHz			–134.2
		10 MHz			–152.6
		100 MHz			–156.2
	Output = 9.8 GHz	100 kHz			–108.2
		1 MHz			–129.1
		10 MHz			–140.5
		100 MHz			–141.1
HARMONIC DISTORTION⁽⁷⁾
HD_fund	Harmonic Distortion fundamental feed-through with doubler enabled	8 GHz, VCO doubler enabled	Fundamental (4 GHz)		–26
HD2	2nd Order Harmonic Distortion⁽⁹⁾	Testing output A, output at 5 GHz, output power level at 8.5-dBm, single-ended output, other end terminated with 50 Ω.			–27		dBc
HD3	3rd Order Harmonic Distortion⁽⁹⁾				–25		dBc
DIGITAL INTERFACE
V_IH	High level input voltage			1.4		V_CC	V
V_IL	Low level input voltage			0		0.4	V
I_IH	High level input current			–25		25	µA
I_IL	Low level input current			–25		25	µA
V_OH	High level output voltage	Load/Source Current of –350 µA			V_CC – 0.4		V
V_OL	Low level output voltage	Load/Sink Current of 500 µA			0.4		V
SPIW	Highest SPI write speed				75		MHz
SPIR	SPI read speed				50		MHz

(1) For typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 6GHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). See the Section 8 section for more information.

(2) For a typical high output power for a single-ended output, with 50-Ω pullup on both M and P side, register OUTx_POW = 63. Un-used side terminated with 50-Ω load.

(3) There is internal voltage biasing so the OSCinM and OSCinP pins must always be AC-coupled (capacitor in series). Vppd is differential peak-to-peak voltage swing. If there is a differential signal (two are negative polarity of each other), the total swing is one subtracted by the other, each should be 0.1 to 1-Vppd. If there is a single-ended signal, it can have 0.2 to 2 Vppd. See the Section 8 section for more information.

(4) To use phase detector frequencies lower than 5-MHz set register FCAL_LPFD_ADJ = 3. To use phase detector frequencies higher than 200 MHz, you must be in integer mode, set register PFD_CTL = 3 (to use single PFD mode), set FCAL_HPFD_ADJ = 3. For more information, see the Section 7 section.

(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10^{PLL_Flat / 10} + 10^{PLL_flicker / 10}).

(6) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift without reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.

(7) Not tested in production. Typical numbers from characterization with output settings: 50-Ω pullup, OUTA_POW = 15, channel divider off.

(8) The is the calibration time from the time of FCAL_EN = 1 is triggered to the calibration algorithm completing and output at 7 GHz. A reference input signal of 100 MHz is used and register CAL_CLK_DIV = 0 for state machine clock to be 100 MHz. Faster calibration times can be achieve through changes of other register settings. See the Section 8 section for more information. This parameter is ensured by bench.

(9) This parameter is verified by characterization on evaluation board, not tested in production.