The N divider (12 bits) includes a multi-stage noise shaping (MASH) sigma-delta modulator with programmable order from 1st to 4th order, which performs fractional compensation and can achieve any fractional denominator from 1 to (2³² – 1). Using programmable registers, PLL_N is the integer portion and PLL_NUM / PLL_DEN is the fractional portion, thus the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows the output frequency to be a fractional multiplication of the phase detector frequency. The higher the denominator the finer the resolution step of the output. There is a N divider prescaler (PLL_N_PRE) between the VCO and the N divider which performs a division of 2 or 4. 2 is selected typically for higher performance in fractional mode and 4 may be desirable for lower power operation and when N is approaching max value.

Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)

Minimum output frequency step = Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]

Typically, higher modulator order pushes the noise out in frequency and may be filtered out with the PLL. However, several tradeoff needs to be made. Table 7-2 shows the suggested minimum N value while in fractional mode as a function of the sigma-delta modulator order. It also describe the recommended register setting for the PFD delay (register PFD_DLY_SEL).