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ZHCSEK3G December 2015 – August 2022 LMX2592

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

6.7 Typical Characteristics

T_A = 25°C (unless otherwise noted)

Figure 6-2 3-GHz Output - Closed-Loop Phase Noise

Figure 6-4 6-GHz Output - Closed-Loop Phase Noise

Figure 6-6 9.8-GHz Output - Closed-Loop Phase Noise

Figure 6-8 Integrated Jitter (49 fs) - 6-GHz Output

Figure 6-10 Variation of Phase Noise Across Temperature

Figure 6-12 High Output Power (50-Ω Pullup, Single-Ended) vs Output Frequency

Figure 6-14 Typical PFD Spur for 5.4-GHz Output

Figure 6-16 Impact of Channel Divider Settings on Phase Noise

Figure 6-3 3-GHz Output - Open-Loop Phase Noise

Figure 6-5 6-GHz Output - Open-Loop Phase Noise

Figure 6-7 9.8-GHz Output - Open-Loop Phase Noise

Figure 6-9 6-GHz Output Wide Loop Bandwidth – Showing PLL Performance

Figure 6-11 Impact of Supply Ripple on 6-GHz Output Phase Noise

Figure 6-13 Output Power at 5.4-GHz Output vs OUTx_POW Code (1 - 31, 48 - 63)

Figure 6-15 20-µs Frequency Change Time to 6 GHz With Fast Calibration

Figure 6-17 Noise Floor Variation With Output Frequency