ZHCSGL5C March 2017 – April 2019 LMX2594
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Reference Oscillator Input
- 7.3.2 Reference Path
- 7.3.3 PLL Phase Detector and Charge Pump
- 7.3.4 N-Divider and Fractional Circuitry
- 7.3.5 MUXout Pin
- 7.3.6 VCO (Voltage-Controlled Oscillator)
- 7.3.7 Channel Divider
- 7.3.8 Output Buffer
- 7.3.9 Power-Down Modes
- 7.3.10 Phase Synchronization
- 7.3.11 Phase Adjust
- 7.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
- 7.3.13 Ramping Function
- 7.3.14 SYSREF
- 7.3.15 SysRefReq Pin
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 General Registers R0, R1, & R7
- 7.6.2 Input Path Registers
- 7.6.3 Charge Pump Registers (R13, R14)
- 7.6.4 VCO Calibration Registers
- 7.6.5 N Divider, MASH, and Output Registers
- 7.6.6 SYNC and SysRefReq Input Pin Register
- 7.6.7 Lock Detect Registers
- 7.6.8 MASH_RESET
- 7.6.9 SysREF Registers
- 7.6.10 CHANNEL Divider Registers
- 7.6.11 Ramping and Calibration Fields
- 7.6.12 Ramping Registers
- 7.6.13 Readback Registers
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
7.3.10.2 Categories of Applications for SYNC
The requirements for SYNC depend on certain setup conditions. In cases that the SYNC is not timing critical, it can be done through software by toggling the VCO_PHASE_SYNC bit from 0 to 1. When it is timing critical, then it must be done through the pin and the setup and hold times for the OSCin pin are critical. Figure 27 gives the different categories.
Figure 27. Determining the SYNC Category