In this mode, the MUXOUT pin will be low when the VCO is calibrating or when the lock detect delay timer is running. Otherwise, the MUXOUT will be high. The programmable timer (LD_DLY, register R60[15:0]) adds an additional delay after the VCO calibration finishes and before the lock detect indicator is asserted high. LD_DLY is a 16-bit unsigned quantity that corresponds to the 4 times the number of phase detector cycles in absolute delay. For example, a phase detector frequency of 100 MHz and the LD_DLY = 10000 will add a delay of 400 µs before the indicator is asserted. This indicator will remain in its current state (high or low) until register R0 is programmed with FCAL_EN = 1 with a valid input reference. In other words, if the PLL goes out of lock or the input reference goes away when the current state is high, then the current state will remain high.