米6体育平台手机版

ZHCSO17C November 2019 – March 2022 LMX2694-SEP

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RTC|48
- MPQF140D

散热焊盘机械数据 (封装 | 引脚)

RTC|48
- QFND642

订购信息

7.6.2 R1 Register (Offset = 0x1) [reset = 0x80C]

R1 is shown in Figure 7-11 and described in Table 7-21.

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Figure 7-11 R1 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0x80

7	6	5	4	3	2	1	0
RESERVED				MUXOUT_CTRL	CAL_CLK_DIV
R/W-0x80				R/W-0x1	R/W-0x4

Table 7-21 R1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R/W	0x80	Program 0x80 to this field.
3	MUXOUT_CTRL	R/W	0x1	Sets the MUXOUT pin status. 0x0 = Tri-state 0x1 = Normal operation
2-0	CAL_CLK_DIV	R/W	0x4	Divides down the f_OSC frequency to the state machine clock frequency. f_SM = f_OSC / (2^CAL_CLK_DIV). Ensure that the state machine clock frequency is 50 MHz or less. 0x0 = f_OSC ≤ 50 MHz 0x1 = 50 MHz < f_OSC ≤ 100 MHz 0x2 = 100 MHz < f_OSC ≤ 200 MHz 0x3 = 200 MHz < f_OSC ≤ 400 MHz 0x4 = 400 MHz < f_OSC ≤ 800 MHz 0x5 = f_OSC > 800 MHz All other values are not used.

Bit

Field

Type

Reset

Description

15-4

RESERVED

R/W

0x80

Program 0x80 to this field.

MUXOUT_CTRL

R/W

0x1

Sets the MUXOUT pin status.

0x0 = Tri-state

0x1 = Normal operation

2-0

CAL_CLK_DIV

R/W

0x4

Divides down the f_OSC frequency to the state machine clock frequency.
f_SM = f_OSC / (2^CAL_CLK_DIV). Ensure that the state machine clock frequency is 50 MHz or less.

0x0 = f_OSC ≤ 50 MHz

0x1 = 50 MHz < f_OSC ≤ 100 MHz

0x2 = 100 MHz < f_OSC ≤ 200 MHz

0x3 = 200 MHz < f_OSC ≤ 400 MHz

0x4 = 400 MHz < f_OSC ≤ 800 MHz

0x5 = f_OSC > 800 MHz

All other values are not used.