8.2.2 Detailed Design Procedure

The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise outside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if loop bandwidth is designed to the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop bandwidth and thus lower jitter. The tradeoff with this is that longer lock times and spurs must be considered in design as well.

As for software programming, it is highly recommended to use the TICSPro software. In addition to simplifying the process, it also gives the user recommended programming default values for the undisclosed registers not mentioned in the datasheet.

Figure 92. PLLatinum Sim Design Example