The LMZ10500 features a transition mode designed to extend the output regulation range to the minimum possible input voltage. As the input voltage decreases closer and closer to V_OUT, the off-time of the PFET gets smaller and smaller and the duty cycle eventually must reach 100% to support the output voltage. The input voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10500 input voltage is lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10500 doubles the switching period to extend the off-time for that V_IN and maintain regulation. If V_IN is lowered even more, the off-time of the PFET will reach the 35ns mark again. The LMZ10500 will then reduce the frequency again, achieving less than 100% duty cycle operation and maintaining regulation. As V_IN is lowered even more, the LMZ10500 will continue to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases further, 100% duty cycle is reached. This behavior of extending the V_IN regulation range is illustrated in Figure 7-3.

Figure 7-3 High Duty Cycle Operation and Switching Frequency Reduction