10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths during PCB layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor C_IN1 is placed a distance away for the LMZ12002. Therefore physically place C_IN1 asa close as possible to the LMZ12002 VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top side plane that connects to the GND exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and enable components must be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R_FBT and R_FBB, and the feed forward capacitor C_FF, must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from R_FBT, R_FBB, and C_FF must be routed away from the body of the LMZ12002 to minimize noise.

4. Make input and output bus connections as wide as possible.

This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with a minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.2 Layout Examples

Figure 40. Critical Current Loops to Minimize

Figure 41. PCB Layout Guide

Figure 42. Top View of Evaluation PCB

Figure 43. Bottom View of Evaluation PCB

10.3 Power Dissipation and Thermal Considerations

For the design case of V_IN = 12 V, V_O = 3.3 V, I_O = 2 A, T_AMB(MAX) = 85°C, and T_JUNCTION = 125°C, the device must see a thermal resistance from case to ambient of:

Given the typical thermal resistance from junction to case to be 1.9°C/W. Use the 85°C power dissipation curves in the Typical Characteristics section to estimate the P_IC-LOSS for the application being designed. In this application it is 1.2 W

To reach R_θCA = 31.4, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is:

As a result, approximately 15.9 square cm of 1-oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the demo board application note AN-2024 (SNVA422).

10.4 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

• Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
  • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
  • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness — 0.125 to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.
• Maximum number of reflows allowed is one

Figure 44. Sample Reflow Profile