The operation of the power good flag function is described in the diagram shown in Figure 7-7.

Figure 7-7 Typical Power Good-Flag Operation

This output consists of an open-drain NMOS with an R_dson of approximately 70 Ω. When used, the power-good flag should be connected to a logic supply through a pullup resistor. It can also be pulled up to either V_IN or V_OUT through an appropriate resistor, as desired. If this function is not needed, the PG output should be left floating. The current through this flag pin should be limited to less than 4 mA. A pullup resistor of greater than or equal to 1.5 kΩ will satisfy this requirement. When the EN input is pulled low, the PG flag output will also be forced low, assuming a valid input voltage is present at the VIN pin.