10.23 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 42 through Figure 45 shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (PVIN, V_OUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place R_SET, R_RT, and C_SS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.

Figure 42. Typical Top-Layer Layout

Figure 44. Typical Layer-3 Layout

Figure 43. Typical Layer-2 Layout

Figure 45. Typical Bottom-Layer Layout