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ZHCSBC7E JULY 2013 – December 2019 LMZ31710

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RVQ|42
- MPQF306C

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6.5 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PV_IN = V_IN = 12 V, V_OUT = 1.8 V, I_OUT = 10 A,
C_IN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, C_OUT = 4 × 47 µF ceramic (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
I_OUT	Output current	T_A = 85°C, natural convection			0⁽¹⁾		10	A
V_IN	Input bias voltage range	Over output current range			4.5		17	V
PV_IN	Input switching voltage range	Over output current range			2.95⁽³⁾		17⁽⁴⁾	V
UVLO	V_IN undervoltage lockout	V_IN Increasing				4	4.5	V
UVLO	V_IN undervoltage lockout	V_IN Decreasing			3.5	3.85		V
V_OUT_(adj)	Output voltage adjust range	Over output current range			0.6		5.5⁽⁵⁾	V
V_OUT	Set-point voltage tolerance	T_A = 25°C, I_OUT = 0 A					±1%⁽²⁾
	Temperature variation	–40°C ≤ T_A ≤ +85°C, I_OUT = 0 A				±0.2%
	Line regulation	Over input voltage range				±0.1%
	Load regulation	Over output current range				±0.2%
	Total output voltage variation	Includes set-point, line, load, and temperature variation					±1.5%⁽²⁾
η	Efficiency	P_VIN = V_IN = 12 V I_O = 5 A	V_OUT = 5 V, f_SW = 1 MHz			93%
			V_OUT = 3.3 V, f_SW = 750 kHz			92%
			V_OUT = 2.5 V, f_SW = 750 kHz			90%
			V_OUT = 1.8 V, f_SW = 500 kHz			89%
			V_OUT = 1.2 V, f_SW = 300 kHz			86%
			V_OUT = 0.9 V, f_SW = 250 kHz			84%
			V_OUT = 0.6 V, f_SW = 200 kHz			81%
		P_V_IN = V_IN = 5 V I_O = 5 A	V_OUT = 3.3 V, f_SW = 750 kHz			94%
			V_OUT = 2.5 V, f_SW = 750 kHz			93%
			V_OUT = 1.8 V, f_SW = 500 kHz			92%
			V_OUT = 1.2 V, f_SW = 300 kHz			89%
			V_OUT = 0.9 V, f_SW = 250 kHz			87%
			V_OUT = 0.6 V, f_SW = 200 kHz			83%
	Output voltage ripple	20 MHz bandwidth				14		mV_P-P
I_LIM	Current limit threshold	ILIM pin open				15		A
I_LIM	Current limit threshold	ILIM pin to AGND				12		A
	Transient response	1 A/µs load step from 25 to 75% I_OUT_(max)		Recovery time		100		µs
	Transient response	1 A/µs load step from 25 to 75% I_OUT_(max)		VOUT over/undershoot		80		mV
V_INH	Inhibit threshold voltage	Inhibit High Voltage			1.3		open⁽⁶⁾	V
V_INH	Inhibit threshold voltage	Inhibit Low Voltage			–0.3		1.1	V
I_INH	INH Input current	V_INH < 1.1 V				-1.15		μA
I_INH	INH Hysteresis current	V_INH > 1.3 V				-3.3		μA
I_I(stby)	Input standby current	INH pin to AGND				2	10	µA
Power Good	PWRGD Thresholds	V_OUT rising		Good		95%
		V_OUT rising		Fault		108%
		V_OUT falling		Fault		91%
		V_OUT falling		Good		104%
	PWRGD Low Voltage	I(PWRGD) = 0.5 mA					0.3	V
ƒ_SW	Switching frequency	R_RT = 169 kΩ			400	500	600	kHz
ƒ_CLK	Synchronization frequency	CLK Control			200		1200	kHz
V_CLK-H	CLK High-Level				2		5.5	V
V_CLK-L	CLK Low-Level						0.5	V
D_CLK	CLK Duty Cycle				20%	50%	80%
	Thermal Shutdown	Thermal shutdown				175		°C
	Thermal Shutdown	Thermal shutdown hysteresis				10		°C
C_IN	External input capacitance	Ceramic			44⁽⁷⁾			µF
C_IN	External input capacitance	Non-ceramic				100⁽⁷⁾		µF
C_OUT	External output capacitance	V_OUT = 0.6 V to 5.5 V		Ceramic	47⁽⁸⁾	200	1500	µF
		V_OUT= 0.6 V to 5.5 V		Non-ceramic		220⁽⁸⁾	5000⁽⁹⁾	µF
		Equivalent series resistance (ESR)					35	mΩ

(1) See Light Load Efficiency (LLE) for more information for output voltages < 1.5 V.

(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R_SET resistor.

(3) The minimum P_VIN is 2.95 V or (V_OUT + 0.7 V), whichever is greater. See Table 7 for more details.

(4) The maximum PV_IN voltage is 17 V or (22 x V_OUT), whichever is less. See Table 7 for more details.

(5) The maximum output voltage may be limited by the power dissipation. The maximum power dissipation of this device is 4.5 W.

(6) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pullup. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.

(7) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.

(8) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance must include at least 1 × 47 µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.

(9) The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors. It may be necessary to increase the slow-start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on adjusting the slow-start time.