SNVS185F February   2002  – April 2017 LP3982

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 No-Load Stability
      2. 7.3.2 Fast Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setting (ADJ Version Only)
        3. 8.2.2.3 Output Capacitance
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Noise Bypass Capacitor
        6. 8.2.2.6 Fault Detection
        7. 8.2.2.7 Power Dissipation
        8. 8.2.2.8 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Layout

Layout Guidelines

Best performance is achieved by placing CIN, COUT, and CCC on the same side of the PCB as the LP3982 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP3982 device GND pin using as wide and as short of a copper trace as is practical.

Avoid connections using long trace lengths and narrow trace widths. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions.

Layout Example

LP3982 WSON_layout_snvs185.gif Figure 21. WSON Package Adjustable Version (Not to Scale)

WSON Mounting

The WSON package requires specific mounting techniques which are detailed in TI Application Report Leadless Leadframe Package (LLP) (SNOA401). Referring to the section PCB Design Recommendations, the pad style which must be used with the WSON package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP. The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device pin 3 (GND). Alternately, but not recommended, the DAP may be left floating (no electrical connection). The DAP must not be connected to any potential other than ground.