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SNVS161E October 2001 – October 2015 LP3988

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

YZR|5
- MXBG268
DBV|5
- MPDS018T

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
IN pin		−0.3	6.5	V
OUT, EN, PG pins		−0.3	See⁽⁴⁾	V
Junction temperature, T_J			150	°C
Power dissipation⁽⁵⁾	SOT-23-5		469	mW
Power dissipation⁽⁵⁾	DSBGA		441	mW
Storage temperature, T_stg		−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

(4) The lesser of V_IN + 0.3 V or 6 V.

(5) The absolute maximum power dissipation depends on the ambient temperature and the R_θJA value; it can be calculated using the formula: P_D = (T_J – T_A)/R_θJA where T_J(MAX) is the maximum junction temperature, T_A(MAX) is the maximum expected ambient temperature, and R_θJA is the junction-to-ambient thermal resistance.The 469-mW rating for the SOT-23-5 package results from substituting the junction temperature, 150°C, for T_J(MAX), 70°C for T_A, and 181.2°C/W for R_θJA. More power can be dissipated safely at ambient temperatures below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The absolute maximum power dissipation can be increased by 5.86 mW for each degree below 70°C, and it must be derated by 5.86 mW for each degree above 70°C. Same principle applies to the DSBGA package.

6.2 ESD Ratings

			VALUE	UNIT
LP3988 IN SOT-23 PACKAGE
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±150	V
LP3988 IN DSBGA PACKAGE
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±200	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_IN		2.5⁽³⁾	6	V
V_OUT, V_EN		0	V_IN	V
V_PG		0	6	V
I_PG		0	500	µA
Junction temperature, T_J		–40	125	°C
Maximum power dissipation⁽⁴⁾	SOT-23		322	mW
Maximum power dissipation⁽⁴⁾	DSBGA		303	mW

(2) All voltages are with respect to the potential at the GND pin.

(3) The minimum V_IN is dependant on the device output option. For V_OUT(NOM) < 2.5 V, V_IN(MIN) equals 2.5 V. For V_OUT(NOM) ≥ 2.5 V, V_IN(MIN) equals V_OUT(NOM) + 200 mV.

(4) Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 322-mW rating appearing under Recommended Operating Conditions for the SOT-23-5 package results from substituting the maximum junction temperature for operation, 125°C, for T_J(MAX), 70°C for T_A(MAX), and 181.2°C/W for R_θJA. More power can be dissipated at ambient temperatures below 70°C . Less power can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 4.5 mW for each degree below 70°C, and it must be derated by 5.86 mW for each degree above 70°C. The same principle applies to the DSBGA package.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP3988		UNIT
		DBV (SOT-23)	YZR (DSBGA)
		5 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance	170.5	181.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	124.4	0.8	°C/W
R_θJB	Junction-to-board thermal resistance	30.9	107.9	°C/W
ψ_JT	Junction-to-top characterization parameter	17.6	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	30.4	107.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise specified: V_EN = 1.8 V, V_IN = V_OUT + 0.5 V, C_IN = 1 µF, I_OUT = 1 mA, C_OUT = 1 µF; typical values and limits are for T_J = 25°C, and minimum and maximum values and limits apply over the entire junction temperature range for operation, −40°C to +125°C.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ΔV_OUT	Output voltage volerance		−2		2	% of V_OUT(NOM)
		−20°C ≤ T_J ≤ 125°C, SOT-23-5	–3		3
		SOT-23-5	–3.5		3.5
		DSBGA	–3		3
	Line regulation error	V_IN = V_OUT(NOM) + 0.5 V to 6 V T_J = 25°C	−0.15		0.15	%/V
	Line regulation error	V_IN = V_OUT(NOM) + 0.5 V to 6 V	–0.2		0.2	%/V
	Load regulation error⁽³⁾	I_OUT = 1 mA to 150 mA, T_J = 25°C			0.005	%/mA
	Load regulation error⁽³⁾	I_OUT = 1 mA to 150 mA			0.007	%/mA
PSRR	Power Supply Rejection Ratio	V_IN = V_OUT(NOM) + 1 V, ƒ = 1 kHz, I_OUT = 50 mA (See Figure 11)		65		dB
PSRR	Power Supply Rejection Ratio	V_IN = V_OUT(nom) + 1 V, ƒ = 10 kHz, I_OUT = 50 mA (See Figure 11)		45		dB
I_Q	Quiescent current	V_EN = 1.4 V, I_OUT = 0 mA, T_J = 25°C		85	120	µA
		V_EN = 1.4 V, I_OUT = 0 to 150 mA		140	200
		V_EN = 0.4 V		0.003	1
	Dropout voltage⁽⁴⁾	I_OUT = 1 mA		1	5	mV
		I_OUT = 150 mA, T_J = 25°C		80	115	mV
		I_OUT = 150 mA			150
I_SC	Short circuit current limit	See⁽⁵⁾		600		mA
e_n	Output noise voltage	BW = 10 Hz to 100 kHz, C_OUT = 1 µF		220		µV_RMS
C_OUT	Output capacitor	Capacitance⁽⁶⁾	1		20	µF
C_OUT	Output capacitor	ESR⁽⁶⁾	5		500	mΩ
TSD	Thermal shutdown temperature			160		°C
TSD	Thermal shutdown hysteresis			20		°C
ENABLE CONTROL CHARACTERISTICS
I_EN	Maximum input current at EN	V_EN = 0 V and V_IN = 6 V			0.1	µA
V_IL	Logic low input threshold	V_IN = 2.5 V to 6 V			0.5	V
V_IH	Logic high input threshold	V_IN = 2.5 V to 6 V	1.2			V
POWER GOOD
V_THL	PG low threshold (See Figure 10)	% of V_OUT (PG ON), T_J = 25°C	90%	93%	95%
V_THH	PG high threshold (See Figure 10)	% of V_OUT (PG OFF), T_J = 25°C⁽⁷⁾	92%	95%	98%
V_OL	PG output logic low voltage	I_PULLUP = 100 µA, fault condition		0.02	0.1	V
I_PGL	PG output leakage current	PG off, V_PG = 6 V		0.02		µA

(1) All electrical characteristics having room-temperature limits are tested during production with T_J = 25°C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) The target output voltage, which is labeled V_OUT(NOM), is the desired voltage option.

(3) An increase in the load current results in a slight decrease in the output voltage and vice versa.

(4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.

(5) Short-circuit current is measured on input supply line after pulling down V_OUT to 95% V_OUT(NOM).

(6) Specified by design. Not production tested. The capacitor tolerance should be ±30% or better over the full temperature range. The full range of operating conditions such as temperature, DC bias and even capacitor case size for the capacitor in the application should be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitor types are recommended to meet the full device temperature range.

(7) The low and high thresholds are generated together. Typically a 2.6% difference is seen between these thresholds.

6.6 Timing Requirements

		MIN	NOM	MAX	UNIT
T_ON	PG turnon time⁽¹⁾, V_IN = 4.2 V		10		µs
T_OFF	PG turnoff time⁽¹⁾, V_IN = 4.2 V		10		µs

(1) Turnon time is time measured between the enable input just exceeding V_IH and the output voltage just reaching 95% of its nominal value.

6.7 Typical Characteristics

Unless otherwise specified, C_IN = C_OUT = 1 µF ceramic, V_IN = V_OUT + 0.2 V, T_A = 25°C, EN pin is tied to V_IN.

Figure 1. Ripple Rejection Ratio (LP3988-2.6 V)

Figure 2. Ripple Rejection Ratio (LP3988-2.6 V)

Figure 3. Power-Good Response Time (LP3988-2.85 V)
(Flag Pin Pulled To V_OUT Through a 100-kΩ Resistor)

Figure 5. Power-Good Response Time (LP3988-2.85 )
(Flag Pin Pulled To V_OUT Through a 100-kΩ Resistor)

Figure 7. Enable Response

Figure 4. Power-Good Response Time (LP3988-2.85 V)
(Flag Pin Pulled To V_IN Through a 100-kΩ Resistor)

Figure 6. Power-Up Response

Figure 8. Enable Response