LP3990 150-mA Linear Voltage Regulator for Digital Applications
- SNVS251J May 2004 – September 2014 LP3990
  
  PRODUCTION DATA.

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DATA SHEET

LP3990 150-mA Linear Voltage Regulator for Digital Applications

1 Features

1% Voltage Accuracy at Room Temperature
Stable with Ceramic Capacitor
Logic Controlled Enable
No Noise Bypass Capacitor Required
Thermal-Overload and Short-Circuit Protection
Input Voltage Range, 2 V to 6 V
Output Voltage Range, 0.8 V to 3.3 V
Output Current, 150 mA
Output Stable - Capacitors, 1 µF
Virtually Zero I_Q (Disabled), < 10 nA
Very Low I_Q (Enabled), 43 µA
Low Output Noise, 150 µV_RMS
PSRR, 55 dB at 1 kHz
Fast Start-Up, 105 µs

2 Applications

Cellular Handsets
Hand-Held Information Appliances

3 Description

The LP3990 regulator is designed to meet the requirements of portable, battery-powered systems providing an accurate output voltage, low-noise, and low-quiescent current. The LP3990 will provide a 0.8-V output from the low input voltage of 2 V at up to a 150-mA load current. When switched into shutdown mode via a logic signal at the enable pin (EN), the power consumption is reduced to virtually zero.

The LP3990 is designed to be stable with space-saving ceramic capacitors with values as low as 1 µF.

Performance is specified for a –40°C to 125°C junction temperature range.

For output voltages other than 0.8 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 2.8 V, or 3.3 V, please contact the Texas Instruments sales office.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP3990	DSBGA (4)	1.324 mm x 1.045 mm (MAX)
	WSON (6)	2.90 mm x 1.60 mm
	SOT-23 (5)	3.00 mm x 3.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

Changes from I Revision (May 2013) to J Revision

Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves sectionGo

5 Pin Configuration and Functions

DSBGA (YZR)

4 Pins

SOT-23 (DBV)

5 Pins

WSON (NGG)

6 Pins

Pin Functions

PIN				I/O	DESCRIPTION
NAME	DSBGA	SOT-23	WSON
NAME	YZR	DBV	NGG
GND	A1	2	2	—	Common Ground.
EN	A2	3	5	I	Enable Input; Enables the Regulator when ≥ 0.95 V. Disables the Regulator when ≤ 0.4 V. Enable Input has 1-MΩ (typical) pull-down resistor to GND.
EN		3	5	I
OUT	B1	5	1	O	Voltage output. A 1-µF Low ESR Capacitor should be connected to this Pin. Connect this output to the load circuit.
IN	B2	1	6	I	Voltage supply Input. A 1-µF capacitor should be connected at this input.
IN	N/A	4	3	I	No internal connection.
N/C		N/A	4	I	No internal connection.
N/C		N/A	Pad	—	Thermal pad. Connect to Pin 2.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾⁽³⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Input voltage	–0.3	6.5	V
Output voltage	–0.3	Note⁽⁴⁾
ENABLE input voltage	–0.3	6.5
Continuous power dissipation internally limited	Note⁽⁵⁾

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) All voltages are with respect to the potential at the GND pin.

(4) The lower of V_IN+ 0.3 V or 6.5 V.

(5) Internal thermal shutdown circuitry protects the device from permanent damage.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	2000	V
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins	250	1500
		Machine model	–200	200

(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Input voltage, V_IN	2	6	V
Enable input voltage, V_EN	0.0	V_IN	V
Junction temperature, T_J⁽¹⁾	–40	125	°C

(1) T_J(max) = (T_A(max) + (R_θJA × P_D(max)) )

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP3990			UNIT
		YZR (DSBGA)	DBV (SOT-23)	NGG (WSON)
		4 PINS	5 PINS	6 PINS
R_θJA	Junction-to-ambient thermal resistance	188.9	165.2	53.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	1.0	69.9	51.2
R_θJB	Junction-to-board thermal resistance	105.3	27.3	28.2
ψ_JT	Junction-to-top characterization parameter	0.7	1.8	0.6
ψ_JB	Junction-to-board characterization parameter	105.2	26.8	28.3
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	8.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics⁽¹⁾⁽³⁾

Unless otherwise noted, V_EN = 950 mV, V_IN = V_OUT + 1 V or V_IN = 2 V, whichever is higher. C_IN = 1 µF, I_OUT = 1 mA, C_OUT = 0.47 µF.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IN	Input voltage	Note ⁽²⁾, T_J = 25°C		2		6	V
ΔV_OUT	Output voltage tolerance	I_LOAD = 1 mA T_J = 25°C	DSBGA	–1		1%
			WQFN	–1.5%		1.5%
			SOT-23	–1.5%		1.5%
		Over full line and load regulation	DSBGA	–2.5%		2.5%
			WQFN	–3%		3%
			SOT-23	–4%		4%
	Line regulation error	V_IN = (V_OUT(NOM) + 1 V) to 6 V		0.1	0.02	0.1	%/V
	Load regulation error	I_OUT = 1 mA to 150 mA	V_OUT = 0.8 V to 1.95 V DSBGA	–0.005	0.002	0.005	%/mA
			V_OUT = 0.8 V to 1.95 V WQFN, SOT-23	–0.008	0.003	0.008
			V_OUT = 2 V to 3.3 V DSBGA	–0.002	0.0005	0.002
			V_OUT = 2 V to 3.3 V WQFN, SOT-23	–0.005	0.002	0.005
V_DO	Dropout voltage	I_OUT = 150 mA⁽⁴⁾⁽⁵⁾			120	200	mV
I_LOAD	Load current	Note ⁽⁵⁾⁽⁶⁾, T_J = 25°C		0			µA
I_Q	Quiescent current	V_EN = 950 mV, I_OUT = 0 mA			43	80	µA
		V_EN = 950 mV, I_OUT = 150 mA			65	120
		V_EN = 0.4 V (output disabled), T_J = 25°C			0.002	0.2
I_SC	Short circuit current limit	Note ⁽⁷⁾			550	1000	mA
I_OUT	Maximum output current			150			mA
PSRR	Power Supply Rejection Ratio	ƒ = 1 kHz, I_OUT = 1 mA to 150 mA			55		dB
PSRR	Power Supply Rejection Ratio	ƒ = 10 kHz, I_OUT = 150 mA			35		dB
e_η	Output noise voltage⁽⁵⁾	BW = 10 Hz to 100 kHz	V_OUT = 0.8 V		60		µV_RMS
			V_OUT = 1.5 V		125
			V_OUT = 3.3 V		180
T_SHUTDOWN	Thermal shutdown junction temperature	Junction temperature (T_J) rising until the output is disabled			155		°C
T_SHUTDOWN	Thermal shutdown junction temperature	Hysteresis			15		°C
ENABLE CONTROL CHARACTERISTICS
I_EN⁽⁸⁾	Maximum input current at EN pin	V_EN = 0 V (Output is disabled) T_J = 25°C			0.001	0.1	µA
I_EN⁽⁸⁾	Maximum input current at EN pin	V_EN = 6 V		2.5	6	10	µA
V_IL	Low input threshold	V_IN = 2 V to 6 V V_EN falling from ≥ V_IH until the output is disabled				0.4	V
V_IH	High input threshold	V_IN = 2 V to 6 V V_EN rising from ≤ V_IL until the output is enabled		0.95			V

(1) All voltages are with respect to the device GND terminal, unless otherwise stated.

(2) V_IN(MIN) = V_OUT(NOM) + 0.5 V, or 2 V, whichever is higher.

(3) Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range (T_J) of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

(4) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value. This parameter applies only for output voltages above 2 V.

(5) This electrical specification is verified by design.

(6) The device maintains the regulated output voltage without the load.

(7) Short-circuit current is measured with V_OUT pulled to 0 V and V_IN worst case = 6 V.

(8) ENABLE Pin has 1-MΩ (typical) resistor connected to GND.

6.6 Output Capacitor, Recommended Specifications⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
C_OUT	Output capacitance	Capacitance⁽³⁾	0.7⁽²⁾	1	500	µF
C_OUT	Output capacitance	ESR	5			mΩ

(1) Unless otherwise specified, values and limits apply for T_J = 25°C.

(2) Limit applies over the full operating junction temperature range (T_J) of −40°C to 125°C.

(3) The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. (See Detailed Design Procedure.)

6.7 Timing Requirements

				NOM⁽¹⁾	MAX⁽²⁾	UNIT
T_ON	Turnon time ⁽³⁾	From V_EN ↑ V_IH to V_OUT 95% level (V_IN(MIN) to 6 V)	V_OUT = 0.8 V	80	150	µs
			V_OUT = 1.5 V	105	200
			V_OUT = 3.3 V	175	250
Transient response	Line transient response (ΔV_OUT)	T_rise = T_fall = 30 µs⁽³⁾, ΔV_IN = 600 mV		8	16	mV (pk-pk)
Transient response	Load transient response (ΔV_OUT)	T_rise = T_fall = 1 µs⁽³⁾, I_OUT = 1 mA to 150 mA C_OUT = 1 µF		55	100	mV

(1) Nom values apply for T_J = 25°C.

(2) Maximum limits apply over the full operating junction temperature (T_J) range of −40°C to 125°C.

(3) This electrical specification is verified by design.

6.8 Typical Performance Characteristics

Unless otherwise specified, C_IN = 1 µF ceramic, C_OUT = 0.47 µF ceramic, V_IN = V_OUT(NOM) + 1 V, T_A = 25°C, V_OUT(NOM) = 1.5 V; V_EN = V_IN.

Figure 1. Output Voltage Change vs Temperature

I_LOAD = 0 mA

Figure 3. Ground Current vs V_IN

I_LOAD = 150 mA

Figure 5. Ground Current vs V_IN

Figure 7. Short Circuit Current

Figure 9. Power Supply Rejection Ratio

Figure 11. Enable Start-Up Time

Figure 2. Ground Current vs Load Current

I_LOAD = 1 mA

Figure 4. Ground Current vs V_IN

Figure 6. Short Circuit Current

Figure 8. Line Transient

Figure 10. Power Supply Rejection Ratio

Figure 12. Noise Density

7 Detailed Description

7.1 Overview

Designed meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is reduced to virtually zero

The LP3990 is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable (EN)

The LP3990 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the V_IH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the V_IL threshold to ensure that the device is fully disabled. If the EN pin is left open the LP3990 output will be disabled.

7.3.2 Thermal Overload Protection (T_SD)

Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

The Thermal Shutdown circuitry of the LP3990 has been designed to protect against temporary thermal overload conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking. Continuously running the LP3990 device into thermal shutdown may degrade device reliability.

7.4 Device Functional Modes

7.4.1 Enable (EN)

The LP3990 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the V_IH threshold to ensure that the device is fully enabled under all operating conditions.

7.4.2 Minimum Operating Input Voltage (V_IN)

The LP3990 does not include any dedicated UVLO circuitry. The LP3990 internal circuitry is not fully functional until V_IN is at least 2 V. The output voltage is not regulated until V_IN ≥ (V_OUT + V_DO), or 2 V, whichever is higher.