7.3.1 Programming

The LP5523 provides flexibility and programmability for dimming and sequencing control. Each LED can be controlled directly and independently through the serial bus, or LED drivers can be grouped together for pre-programmed flashing patterns.

The LP5523 has three independent program execution engines, so it is possible to form three independently programmable LED banks. LED drivers can be grouped based on their function so that, for example, the first bank of drivers can be assigned to the keypad illumination, the second bank to the funlights, and the third group to the indicator LED(s).

Each bank can contain 1 to 9 LED driver outputs. Instructions for program execution engines are stored in the program memory. The total amount of the program memory is 96 instructions, and the user can allocate the memory as required by the engines.

7.3.2 LED Error Detection

The LP5523 has built-in LED error detection. Error detection does not only detect open and short circuit, but provides an opportunity to measure the V_F of the LEDs. The test event is activated by a serial interface write, and the results can be read through the serial interface during the next cycle. This feature can also be addressed to measure the voltage on VDD, VOUT, and INT pins. Typical example usage includes monitoring battery voltage or using INT pin as a light sensor interface.

7.3.3 Energy Efficiency

When charge-pump automatic mode selection is enabled, the LP5523 monitors the voltage over the drivers of D1 to D6 so that the device can select the best charge-pump gain and maintain good efficiency over the whole operating voltage range. The red LED element of an RGB LED typically has a forward voltage of about 2 V. For that reason, the outputs D7, D8, and D9 are internally powered by V_DD, since battery voltage is high enough to drive red LEDs over the whole operating voltage range. This allows the driving of three RGB LEDs with good efficiency because the red LEDs do not load the charge pump. The LP5523 is able to automatically enter power-save mode when LED outputs are not active, thus lowering idle current consumption down to 10 µA (typical). Also, during the down time of the PWM cycle (constant current output status is low), additional power savings can be achieved when the PWM Powersave feature is enabled.

7.3.4 Temperature Compensation

The luminance of an LED is typically a function of its temperature even though the current flowing through the LED remains constant. Because luminance is temperature dependent, many LED applications require some form of temperature compensation to decrease luminance and color purity variations due to temperature changes. The LP5523 has a built-in temperature-sensing element, and PWM duty cycle of the LED drivers changes linearly in relationship to changes in temperature. User can select the slope of the graph (31 slopes) based on the LED characteristics (see Figure 13). This compensation can be done either constantly, or only right after the device wakes up from power-save mode, to avoid error due to self-heating of the device. Linear compensation is considered to be practical and accurate enough for most LED applications.

Figure 13. Temperature Compensation Principle

Compensation is effective over the temperature range −40°C to +90°C.

7.3.5 Charge Pump Operational Description

7.3.5.2 Output Resistance

At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (R_OUT) of the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump shown in Figure 14.

Figure 14. Charge Pump Output Resistance Model

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5×), and an output resistance (R_OUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The output resistance is 3.5 Ω (typical), and it is a function of switching frequency, input voltage, capacitance value of the flying capacitor, internal resistances of the switches, and ESR of the flying capacitors. When the output voltage is in regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5 V (typical).

With increased output current, the voltage drop across R_OUT increases. To prevent drop in output voltage, the voltage drop across the regulator is reduced, V’ increases, and V_OUT remains at 4.5 V. When the output current increases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and the output voltage is on the edge of regulation. Additional output current causes the output voltage to fall out of regulation, so that the operation is similar to a basic open-loop 1.5× charge pump. In this mode, output current results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation output voltage can be approximated by: V_OUT = 1.5 × V_IN – I_OUT × R_OUT.

7.3.5.5 Gain Change Hysteresis

Charge-pump-gain control utilizes digital filtering to prevent supply voltage disturbances (for example, the transient voltage on the power supply during the GSM burst) from triggering unnecessary gain changes. Hysteresis is provided to prevent periodic gain changes (which could occur due to LED driver) and charge-pump voltage drop in 1× mode. The hysteresis of the gain change is user-configurable; default setting is factory-programmable. Flexible configuration ensures that hysteresis can be minimized or set to desired level in each application.

LED forward voltage monitoring and gain control block diagram is shown in Figure 15.

Figure 15. Forward Voltage Monitoring and Gain Control Block

7.3.6 LED Driver Operational Description

7.3.6.1 Overview

The LP5523 LED drivers are constant-current sources. Output current can be programmed by control registers up to 25.5 mA. The overall maximum current is set by 8-bit output current control registers with 100-μA step size. Each of the 9 LED drivers has a separate output-current control register.

The LED luminance pattern (dimming) is controlled with PWM (pulse width modulation) technique, which has internal resolution of 12 bits (8-bit control can be seen by user). PWM frequency is 312 Hz. See Figure 16.

Figure 16. LED Pattern and Current Control Principle

LED dimming is controlled according to a logarithmic or linear scale, see Figure 17. A logarithmic or linear scheme can be set for both the program execution engine control and direct PWM control. Note: if the temperature compensation is active, the maximum PWM duty cycle is limited to 50% at 25°C. This is required to allow enough headroom for temperature compensation over the whole temperature range −40°C to +90°C.

Figure 17. Logarithmic vs Linear Dimming

7.4.1 Modes Of Operation

7.4.1.2 PWM Power-Save Mode

PWM cycle power-save mode is enabled when register 36 bit [2] PWM_PS_EN is set to 1. In PWM power-save mode analog blocks are powered down during the "down time" of the PWM cycle. Which blocks are powered down depends whether the external or internal clock is used. While the Automatic Power-Save Mode (see above) saves energy when there is no PWM activity at all, the PWM power-save mode saves energy during PWM cycles. Like the automatic power-save mode, PWM power-save mode also works during program execution. Figure 18 shows the principle of the PWM power-save technique. An LED on D9 output is driven at 50% PWM, 5-mA current (top waveform). After PWM Power-save enable, the LED-current remains the same, but the LP5523 input current drops down to an approximately 50-µA level when the LED is OFF, or to an approximately 200-µA level when the charge-pump-powered output(s) are used.

Figure 18. PWM Power-Save Principle; External Clock, V_DD = 3.6 V

7.5.1 I²C-Compatible Control Interface

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data transfer.

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW.

Figure 19. Data Validity Diagram

7.5.1.4 I²C-Compatible Chip Address

ASEL0 and ASEL1 pins configure the chip address for the LP5523 as shown in Table 1.

Table 1. LP5523 Chip Address Configuration

ASEL1	ASEL0	ADDRESS	8-BIT HEX ADDRESS
		(HEX)	WRITE/READ
GND	GND	32	64/65
GND	VEN	33	66/67
VEN	GND	34	68/69
VEN	VEN	35	6A/6B

Figure 20. LP5523 Chip Address

This data pattern writes temperature information to the TEMPERATURE WRITE register (40h).

Figure 21. Write Cycle (W = Write; SDA = 0), Id = Chip Address = 32h for LP5523

This data pattern reads temperature information from the TEMPERATURE READ register (3Fh). When a READ function is to be accomplished, a WRITE function must precede the READ function.

Figure 22. Read Cycle (R = Read; SDA = 1), Id = Chip Address = 32h for LP5523

7.5.1.4.1 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes, the slave’s control register address is incremented by one after acknowledge signal. In order to reduce program load time, the LP5523 supports address auto incrementation. Register address is incremented after each 8 data bits. For example, the whole program memory page can be written in one serial bus write sequence. Note: serial bus address auto increment is not supported for register addresses from 16 to 1E.
• Write cycle ends when the master creates stop condition.

7.5.1.4.2 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends an acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition

7.5.1.4.3 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP5523, the internal address index counter is incremented by one, and the next register is written. Example below (Table 2) shows writing sequence to two consecutive registers. Auto-increment feature is enabled by writing EN_AUTO_INCR bit high in the MISC register (addr 36h). Note: serial bus address auto increment is not supported for register addresses from 16 to 1E.

Table 2. Auto Increment Example.

MASTER	START	CHIP ADDR =32H	WRITE		REG ADDR		DATA		DATA		STOP
LP5523				ACK		ACK		ACK		ACK

7.6.1 Register Set

The LP5523 is controlled by a set of registers through the two-wire serial interface port. Some register bits are reserved for future use. Table 3 lists device registers, their addresses and their abbreviations. A more detailed description is given in Control Register Details.

7.6.2 Control Register Details

00 ENABLE/ ENGINE CONTROL1

• 00 - Bit [6] CHIP_EN
  • 1 = internal start-up sequence powers up all the needed internal blocks and the device enters normal mode.
  • 0 = standby mode is entered. Control registers can still be written or read, excluding bits[5:0] in reg 00 (this register), registers 16h to 1E (LED PWM registers) and 37h to 39h (program counters).
• 00 — Bits [5:4] ENGINE1_EXEC
  • Engine 1 program execution control. Execution register bits define how the program is executed. Program start address can be programmed to Program Counter (PC) register 37H.
  • 00 = hold: Hold causes the execution engine to finish the current instruction and then stop. Program counter (PC) can be read or written only in this mode.
  • 01 = step: Execute the instruction at the location pointed by the PC, increment the PC by one and then reset ENG1_EXEC bits to 00 (i.e. enter hold).
  • 10 = free run: Start program execution from the location pointed by the PC.
  • 11 = execute once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00 (that is, enter hold). The difference between step and execute once is that execute once does not increment the PC.
• 00 — Bits [3:2] ENGINE2_EXEC
  • Engine 2 program execution control. Equivalent to above definition of control bits. Program start address can be programmed to PC register 38H.
• 00 — Bits [1:0] ENGINE3_EXEC
  • Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can be programmed to PC register 39H.

01 ENGINE CONTROL2

• Operation modes are defined in this register.
  • Disabled: Engines can be configured to disabled mode each one separately.
  • Load program: Writing to program memory is allowed only when the engine is in load program operation mode and engine busy bit (reg 3A) is not set. Serial bus master should check the busy bit before writing to program memory or allow at least 1ms delay after entering to load mode before memory write, to ensure initalization. All the three engines are in hold while one or more engines are in load program mode. PWM values are frozen, also. Program execution continues when all the engines are out of load program mode. Load program mode resets the program counter of the respective engine. Load program mode can be entered from the disabled mode only. Entering load program mode from the run program mode is not allowed.
  • Run Program:Run program mode executes the instructions stored in the program memory. Execution register (ENG1_EXEC etc.) bits define how the program is executed (hold, step, free run or execute once). Program start address can be programmed to the PC register. The PC is reset to zero when the PC’s upper limit value is reached.
  • Halt: Instruction execution aborts immediately, and engine operation halts.
  • 01 — Bit [5:4] ENGINE1_MODE
  • 00 = disabled.
  • 01 = load program to SRAM, reset engine 1 PC.
  • 10 = run program as defined by ENGINE1_EXEC bits.
  • 11 = halts the engine.
  • 01 — Bits [3:2] ENGINE2_MODE
  • 00 = disabled.
  • 01 = load program to SRAM, reset engine 2 PC.
  • 10 = run program as defined by ENGINE2_EXEC bits.
  • 11 = halts the engine.
  • 01 — Bits [3:2] ENGINE3_MODE
  • 00 = disabled.
  • 01 = load program to SRAM, reset engine 3 PC.
  • 10 = run program as defined by ENGINE3_EXEC bits.
  • 11 = halts the engine.

02 OUTPUT DIRECT/RATIOMETRIC MSB

A particular feature of the LP5523 is the ratiometric up/down dimming of the RGB LEDs. In other words, the LED driver PWM output varies in a ratiometric manner. By a ratiometric approach the emitted color of an RGB LED remains the same regardless of the initial magnitudes of the R/G/B PWM outputs. For example, if the PWM output of the red LED output is doubled, the output of green LED is doubled also.

• 02 — Bit [0] D9_RATIO_EN
  • 1 = enables ratiometric dimming for D9 output.
  • 0 = disables ratiometric dimming for D9 output.

03 OUTPUT DIRECT/RATIOMETRIC LSB

• 03 — Bit [7] D8_RATIO_EN
  • 1 = enables ratiometric dimming for D8 output.
  • 0 = disables ratiometric dimming for D8 output.
• 03 — Bit [0] D1_RATIO_EN to Bit [6] D7_RATIO_EN
  • The options for D1 output to D7 output are the same as previous: see 03 — Bit [7].

04 OUTPUT ON/OFF CONTROL MSB

• 04 — Bit [0] D9_ON
  • 1 = D9 output ON.
  • 0 = D9 output OFF.
  • Note: Engine mapping overrides this control.

05 OUTPUT ON/OFF CONTROL MSB

• 05 — Bit [7] D8_ON
  • 1 = D8 output ON.
  • 0 = D8 output OFF.
  • Note: Engine mapping over rides this control.
• 05 — Bit [0] D1_ON to Bit [6] D7_ON
  • The options for D1 output to D7 output are the same as above — see the “05 — Bit [7]” section.

06 D1 CONTROL

This is the register used to assign the D1 output to the MASTER FADER group 1, 2, or 3, or none of them. Also, this register sets the correction factor for the D1 output temperature compensation and selects between linear and logarithmic PWM brightness adjustment. By using logarithmic PWM-scale the visual effect looks like linear. When the logarithmic adjustment is enabled, the device handles internal PWM values with 12-bit resolution. This allows very fine-grained PWM control at low PWM duty cycles.

• 06 — Bit [7:6] MAPPING
  • 00 = no master fader set, clears master fader set for D1. Default setting.
  • 01 = MASTER FADER1 controls the D1 output.
  • 10 = MASTER FADER2 controls the D1 output.
  • 11 = MASTER FADER3 controls the D1 output.
  • The duty cycle on D1 output is the D1 PWM register value (address 16H) multiplied with the value in the MASTER FADER register.
• 06 — Bit [5] LOG_EN
  • 0 = linear adjustment.
  • 1 = logarithmic adjustment.
  • This bit is effective for both the program execution engine control and direct PWM control.
• 06 — Bit [4:0] TEMP_COMP
  • The reference temperature is 25°C (that is, the temperature at which the compensation has no effect) and the correction factor (slope) can be set in 0.1% 1/°C steps to any value between −1.5% 1/°C and +1.5% 1/°C, with a default to 0.0% 1/°C.

  TEMP_COMP BITS	CORRECTION FACTOR (%)
  00000	Not activated - default setting after reset.
  11111	−1.5 1/°C
  11110	−1.4 1/°C
  ...	...
  10001	−0.1 1/°C
  10000	0 1/°C
  00001	+0.1 1/°C
  ...	...
  01110	+1.4 1/°C
  01111	+1.5 1/°C

The PWM duty cycle at temperature T (in centigrade) can be obtained as follows: PWM_F = [PWM_S – (25 – T) × correction factor × PWM_S] / 2, where PWM_F is the final duty cycle at temperature T, PWM_S is the set PWM duty cycle (PWM duty cycle is set in registers 16H to 1EH) and the value of the correction factor is obtained from the table above.

For example, if the set PWM duty cycle in register 16H is 90%, temperature T is −10°C, and the chosen correction factor is 1.5% 1/°C, the final duty-cycle PWM_F for D1 output is [90% – (25°C − (−10°C)) × 1.5% 1/°C × 90%] / 2 = [90% – 35 × 0.015 × 90%] / 2 = 21.4%. Default setting 00000 means that the temperature compensation is non-active and the PWM output (0 to 100%) is set solely by PWM registers D1 PWM to D9 PWM.

07 D2 CONTROL to 0E D9 CONTROL

• The control registers and control bits for D2 output to D9 output are similar to that given to D1, see previous 06 – Bit [5] and 06 – Bits [4:0].

16 D1 PWM

• This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation; direct PWM control is active after power up by default. Note: serial bus address auto increment is not supported for register addresses from 16 to 1E.
  • 16 — Bits [7:0] PWM
    • These bits set the D1 output PWM as shown in Figure 23. Note: if the temperature compensation is active, the maximum PWM duty cycle is 50% at 25°C. This is required to allow enough headroom for temperature compensation over the temperature range −40°C to +90°C.
    Figure 23. Direct PWM Control Bits vs PWM Duty Cycle

17 D2 PWM to 1E D9 PWM

• PWM duty cycle control for outputs D2 to D9. The control registers and control bits for D2 output to D9 output are similar to that given to D1.

26 D1 CURRENT CONTROL

• D1 LED driver output current control register. The resolution is 8-bits and step size is 100 μA.

27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL

• The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.

36 MISC

• This register contains miscellaneous control bits.
  • 36 — Bit [7] VARIABLE_D_SEL
    • Variable D source selection
    • 1 = variable D source is the LED test ADC output (LED TEST ADC). This allows, for example, program execution control with analog signal.
    • 0 = variable D source is the register 3C (VARIABLE).
  • 36 — Bit [6] EN_AUTO_INCR
    • The automatic increment feature of the serial bus address enables a quick memory write of successive registers within one transmission.
    • 1 = serial bus address automatic increment is enabled.
    • 0 = serial bus address automatic increment is disabled.
  • 36 — Bit [5] POWERSAVE_EN
    • 1 = power save mode is enabled.
    • 0 = power save mode is disabled. See Automatic Power-Save Mode for further details.
  • 36 — Bits [4:3] CP_MODE
    • Charge-pump-operation mode
    • 00 = OFF
    • 01 = forced to bypass mode (1×)
    • 10 = forced to 1.5× mode; output voltage is boosted to 4.5 V
    • 11 = automatic mode selection
  • 36 — Bit [2] PWM_PS_EN
    • Enables PWM power-save operation. Significant power savings can be achieved, for example, during ramp instruction.
  • 36 — Bits [1:0] CLK_DET_EN and INT_CLK_EN
    • Program execution is clocked with internal 32.7-kHz clock or with an external clock. Clocking is controlled with bits INT_CLK_EN and CLK_DET_EN in the following way:
    • 00 = forced external clock (CLK pin).
    • 01 = forced internal clock.
    • 10 = automatic selection.
    • 11 = internal clock.
    • External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32.7 kHz for correct operation. If a higher or a lower frequency is used, it affects the program execution engine operation speed. The detector block does not limit the maximum frequency. External clock status can be checked with read only bit EXT_CLK_USED in register address 3A, when the external clock detection is enabled (Bit [1] CLK_DET_EN = high).
    • If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on this pin and extra current consumption.

37 ENGINE1 PC

• Program counter starting value for program execution engine 1; a value from 0000000 to 1011111. The maximum value depends on program memory allocation between the three program execution engines.

38 ENGINE2 PC

• 38 — Bits [6:0] PC
  • Program counter starting value for program execution engine 2; a value from 0000000 to 1011111.

39 ENGINE3 PC

• 39 — Bits [6:0] PC
  • Program counter starting value for program execution engine 3; a value from 0000000 to 1011111.

3A STATUS/INTERRUPT

• 3A — Bit [7] LEDTEST_MEAS_DONE
  • This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register. Typically the conversion takes 2.7 milliseconds to complete.
  • 1 = LED test done.
  • 0 = LED test not done.
  • This bit is a read-only bit, and it is cleared (to 0) automatically after a read operation.
• 3A — Bit [6] MASK_BUSY
  • Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.
  • 1 = Interrupt events are masked; that is, no external interrupt is generated from STARTUP_BUSY or ENGINE_BUSY event (default).
  • 0 = External interrupt are generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer true. Reading the register 3A clears the status bits [5:4] and releases INT pin to high state.
• 3A — Bit [5] STARTUP_BUSY
  • A status bit which indicates that the device is running the internal start-up sequence. See Modes Of Operation for details.
  • 1 = internal start-up sequence running Note: STARTUP_BUSY = 1 always when CHIP_EN bit is 0.
  • 0 = internal start-up sequence completed
• 3A — Bit [4] ENGINE_BUSY
  • A status bit which indicates that a program execution engine is clearing internal registers. Serial bus master should not write or read program memory, or registers 00H, 37H to 39H or 4CH to 4EH, when this bit is set to 1.
  • 1 = at least one of the engines is clearing internal registers
  • 0 = engine ready
• 3A — Bit [3] EXT_CLK_USED
  • 1 = external clock detected
  • 0 = external clock not detected
  • This bit is high when external clock signal on CLK pin is detected. CLK_DET_EN bit high in address 36 enables the clock detection.
• 3A — Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT
  • 1 = interrupt set.
  • 0 = interrupt unset/cleared.
  • Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END or INT instruction. Reading the interrupt bit clears the interrupt.

3B GPO

The LP5523 has one general purpose output pin (GPO). The status of the pin can be controlled with this register. Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configured to function as a GPO, output level is defined by the V_DD voltage.

• 3B — Bit [2] INT_CONF
  • 0 = INT pin is set to function as an interrupt pin (default).
  • 1 = INT pin is configured to function as a GPO.
• 3B — Bit [1] GPO
  • 0 = GPO pin state is low.
  • 1 = GPO pin state is high.
  • GPO pin is a digital CMOS output, and no pulldown resistor is needed.
• 3B — Bit [0] INT_GPO
  • 0 = INT pin state is low (if INT_CONF = 1).
  • 1 = INT pin state is high (if INT_CONF = 1).
  • When the GPO function of the INT pin is disabled, it operates as an open drain pin. INT signal is active low; that is, when an interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed for proper functionality.

3C VARIABLE

• 3C — Bits [7:0] VARIABLE
  • These bits are used for storing a global 8-bit variable. Variable can be used to control program flow.

3D RESET

• 3D — Bits [7:0] RESET
  • Writing 11111111 into this register resets the LP5523. Internal registers are reset to the default values. Reading RESET register returns 00000000.

3E TEMP ADC CONTROL

• 3E — Bit [7] TEMP_MEAS_BUSY
  • 1 = temperature measurement active
  • 0 = temperature measurement done or not activated
• 3E — Bit [2] EN_TEMP_SENSOR
  • 1 = enables internal temperature sensor. Every time when EN_TEMP_SENSOR is written high a new measurement period is started. The length of the measurement period depends on temperature. At 25°C a measurement takes 20 milliseconds. Temperature can be read from register 3F.
  • 0 = temp sensor disabled
• 3E — Bit [1] CONTINUOUS _CONV
  • This bit is effective when EN_TEMP_SENSOR = 1.
  • 1 = continuous temperature measurement. Not active when the device is in power save.
  • 0 = new temperature measurement period initiated during start-up or after exit from power-save mode.

• 3E — Bit [0] SEL_EXT_TEMP
  • 1 = temperature compensation source register addr 40H
  • 0 = temperature compensation source register addr 3FH

3F TEMPERATURE READ

• 3F — Bits [7:0] TEMPERATURE
  • These bits are used for storing an 8-bit temperature reading acquired from the internal temperature sensor. This register is a read-only register. Temperature reading is stored in 8-bit two's complement format — see the following table:

  TEMPERATURE READ BITS	TEMPERATURE INTERPRETATION (TYPICAL) (°C)
  11010111	−41
  11011000	−40
  ...	...
  11111110	−2
  11111111	−1
  00000000	0
  00000001	1
  00000010	2
  ...	...
  01011000	88
  01011001	89

40 TEMPERATURE WRITE

• 40 — Bits [7:0] TEMPERATURE
  • These bits are used for storing an 8-bit temperature reading acquired from an external sensor, if such a sensor is used. Temperature reading is stored in 8-bit two's complement format, like in 3F TEMPERATURE READ register.

  NOTE

  When writing temperature data outside the range of the temperature compensation: Values greater than 89°C are set to 89°C; values less than −39°C are set to −39°C.

41 LED TEST CONTROL

• LED test control register
  • 41 — Bit [7] EN_LEDTEST_ADC
  • Writing this bit high (1) fires single LED test conversion. LED test measurement cycle is 2.7 milliseconds.
• 41 — Bit [6] EN_LEDTEST_INT
  • 1 = interrupt signal is sent to the INT pin when the LED test is accomplished.
  • 0 = no interrupt signal is sent to the INT pin when the LED test is accomplished.
  • Interrupt can be cleared by reading STATUS/INTERRUPT register 3A.
• 41 — Bit [5] CONTINUOUS_CONV
  • 1 = continuous LED test measurement. Not active in power-save mode.
  • 0 = continuous conversion is disabled.
• 41 — Bits [4:0] LED__TEST_CTRL
  • These bits are used for choosing the LED driver output to be measured. V_DD, INT-pin, and charge-pump output voltage can be measured, also.

42 LED TEST ADC

• 42 — Bits [7:0] LED_TEST_ADC
  • This is used to store the LED test result. Read-only register. LED test ADC's least significant bit corresponds to 30 mV. The measured voltage V (typical) is calculated as follows: V = (RESULT(DEC) × 0.03 – 1.478 V. For example, if the result is 10100110 = 166(DEC), the measured voltage is 3.5 V (typical). See Figure 24.

Figure 24. LED Test Results vs Measured Voltage

45 ENGINE1 VARIABLE A

• 45 — Bits [7:0] VARIABLE FOR ENGINE1
  • These bits are used for Engine 1 local variable. Read-only register.

46 ENGINE2 VARIABLE A

• 46 — Bits [7:0] VARIABLE FOR ENGINE2
  • These bits are used for Engine 2 local variable. Read-only register.

47 ENGINE3 VARIABLE A

• 47 — Bits [7:0] VARIABLE FOR ENGINE3
  • These bits are used for Engine 3 local variable. Read-only register.

48 MASTER FADER1

• 48 — Bits [7:0] MASTER_FADER
  • An 8-bit register to control all the LED-drivers mapped to MASTER FADER1. Master fader allows the user to control dimming of multiple LEDS with a single serial bus write. This is a faster method to control the dimming of multiple LEDs compared to the dimming done with the PWM registers (address 16H to 1EH), which would need multiple writes.

49 MASTER FADER2

• 49 — Bits [7:0] MASTER_FADER
  • An 8-bit register to control all the LED-drivers mapped to MASTER FADER2. See MASTER FADER1 description.

4A MASTER FADER3

• 4A — Bits [7:0] MASTER_FADER
  • An 8-bit register to control all the LED-drivers mapped to MASTER FADER3. See MASTER FADER1 description.

4C ENG1 PROG START ADDR

• Program memory allocation for program execution engines is defined with PROG START ADDR registers.
  • 4C — Bits [6:0] — ADDR
  • Engine 1 program start address.

4D ENG2 PROG START ADDR

• 4D — Bits [6:0] — ADDR
  • Engine 2 program start address.

4E ENG3 PROG START ADDR

• 4E — Bits [6:0] — ADDR
  • Engine 3 program start address.

4F PROG MEM PAGE SELECT

• 4F — Bits [2:0] — PAGE_SEL
  • These bits select the program memory page. The program memory is divided into six pages of 16 instructions; thus, the total amount of the program memory is 96 instructions.

70H ENG1 MAPPING MSB

• Valid engine 1-to-LED -mapping information can be read from ENG1 MAPPING register.
• 70H — Bit [7] GPO
  • 1 = GPO pin is mapped to the program execution engine 1.
  • 0 = GPO pin non-mapped to the program execution engine 1.
• 70H — Bit [0] D9
  • 1 = D9 pin is mapped to the program execution engine 1.
  • 0 = D9 pin non-mapped to the program execution engine 1.

71H ENG1 MAPPING LSB

• 71H — Bit [7] D8
  • 1 = D8 pin is mapped to the program execution engine 1.
  • 0 = D8 pin non-mapped to the program execution engine 1.
• 71H — Bit [6] D7
  • 1 = D7 pin is mapped to the program execution engine 1.
  • 0 = D7 pin non-mapped to the program execution engine 1.
• 71H — Bit [5] D6
  • 1 = D6 pin is mapped to the program execution engine 1.
  • 0 = D6 pin non-mapped to the program execution engine 1.
• 71H — Bit [4] D5
  • 1 = D5 pin is mapped to the program execution engine 1.
  • 0 = D5 pin non-mapped to the program execution engine 1.
• 71H — Bit [3] D4
  • 1 = D4 pin is mapped to the program execution engine 1.
  • 0 = D4 pin non-mapped to the program execution engine 1.
• 71H — Bit [2] D3
  • 1 = D3 pin is mapped to the program execution engine 1.
  • 0 = D3 pin non-mapped to the program execution engine 1.
• 71H — Bit [1] D2
  • 1 = D2 pin is mapped to the program execution engine 1.
  • 0 = D2 pin non-mapped to the program execution engine 1.
• 71H — Bit [0] D1
  • 1 = D1 pin is mapped to the program execution engine 1.
  • 0 = D1 pin non-mapped to the program execution engine 1.

72H ENG2 MAPPING MSB

• Valid engine 2-to-LED-mapping information can be read from ENG2 MAPPING register.
• 72H — Bit [7] GPO
  • See description above for ENG1 MAPPING register.
• 72H — Bit [0] D9
  • See previous description for ENG1 MAPPING register.

73H ENG2 MAPPING LSB

• 73H — Bit [7] D8 to Bit [0] D1
• See previous description for ENG1 MAPPING register.

74H ENG3 MAPPING MSB

• Valid engine 3-to-LED -mapping information can be read from ENG3 MAPPING register.
• 74H — Bit [7] GPO
  • See description above for ENG1 MAPPING register.
• 74H — Bit [0] D9
  • See description above for ENG1 MAPPING register.

75H ENG3 MAPPING LSB

• 75H — Bit [7] D8 to Bit [0] D1
  • See previous description for ENG1 MAPPING register.

76H GAIN_CHANGE_CTRL

• With hysteresis and timer bits the user can optimize the charge pump performance to better meet the requirements of the application at hand. Some applications need to be optimized for efficiency and others need to be optimized for minimum EMI, for example.
• 76H - Bits[7:6] THRESHOLD
  • Threshold voltage (typical) pre-setting. Bits set the threshold voltage at which the charge-pump gain changes from 1.5× to 1×. The threshold voltage is defined as the voltage difference between highest voltage output (D1 to D6) and input voltage V_DD: V_THRESHOLD = V_DD – MAX(voltage on D1 to D6).
  • If V_THRESHOLD is larger than the set value (100 mV to 400 mV), the charge pump is in 1× mode.
  • 00 = 400 mV
  • 01 = 300 mV
  • 10 = 200 mV
  • 11 = 100 mV

NOTE

Values above are typical and should not be used as product-specification.

NOTE

Writing to threshold [7:6] bits by the user overrides factory settings. Factory settings aren't user-accessible.

• 76H - Bit [5] ADAPTIVE_TRESH_EN
  • 1 = Adaptive threshold enabled.0 = Adaptive threshold disabled.
  • 0 = Adaptive threshold disabled.

  Gain-change hysteresis prevents the mode from toggling back and forth (1× -> 1.5× -> 1x...) , which would cause ripple on V_IN and LED flicker. When the adaptive threshold is enabled, the width of the hysteresis region depends on the choice of threshold bits (see above), saturation of the current sources, charge pump load current, PWM overlap and temperature.

• 76H - Bits [4:3] TIMER
• A forced mode change from 1.5× to 1× is attempted at the interval specified with these bits. Mode change is allowed if there is enough voltage over the LED drivers to ensure proper operation. Set FORCE_1x to 1 (see following 76H - Bit [2] FORCE_1x) to activate this feature.
  • 00 = 5 ms
  • 01 = 10 ms
  • 10 = 50 ms
  • 11 = infinite. The charge pump switches gain from 1× mode to 1.5× mode only. The gain reset back to 1× is enabled under certain conditions, for example in the powersave mode.
• Activates forced mode change. In forced mode, charge pump mode change from 1.5× to 1× is attempted at the constant interval specified with the TIMER bits.
  • 1 = forced-mode changes enabled
  • 0 = forced-mode changes disabled

7.6.3 Instruction Set

The LP5523 has three independent programmable execution engines. All the program execution engines have their own program memory block allocated by the user. Note that in order to access program memory the operation mode needs to be load program, at least for one of the three program execution engines. Program execution is clocked with a 32.7-kHz clock. This clock can be generated internally or external 32-kHz clock can be connected to CLK pin. Using external clock enables synchronization of LED timing to the external clock signal.

Supported instruction set is listed in the following tables:

7.6.4 LED Driver Instructions

7.6.4.2 Ramp Instruction Application Example

Suppose that the LED dimming is controlled according to the linear scale and effective PWM value at the moment t = 0 is 140d (approximately 55%), as shown in Figure 25, and goal is to reach a PWM value of 148d (approximately 58%) at the moment t = 1.5 s. The parameters for the RAMP instruction are:

• Prescale = 1 → 15.625 ms cycle time
• Step time = 12 → step time span is 12 × 15.625 ms = 187.5 ms
• Sign = 0 → increase PWM output
• # of increments = 8 → take 8 steps

Figure 25. Example of Ramp Instruction

7.6.5 LED Mapping Instructions

These instructions define the engine-to-LED mapping. The mapping information is stored in a table, which is stored in the SRAM (program memory of the LP5523). LP5523 has three program execution engines which can be mapped to 9 LED drivers or to one GPO pin. One engine can control one or multiple LED drivers. There are totally eleven instructions for the engine-to-LED-driver control: mux_ld_start, mux_map_start, mux_ld_end, mux_sel, mux_clr, mux_map_next, mux_map_prev, mux_ld_next, mux_ld_prev, mux_ld_addr and mux_map_addr.

MUX_LD_START; MUX_LD_END

Mux_ld_start and mux_ld_end define the mapping table location in the memory.

MUX_MAP_START

Mux_map_start defines the mapping table start address in the memory, and the first row of the table is activated (mapped) at the same time.

MUX_SEL

With mux_sel instruction one, and only one, LED driver (or the GPO-pin) can be connected to a program execution engine. Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been released from an LED, PWM register value still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_CLR

Mux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM register value still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_MAP_NEXT

This instruction sets the next row active in the mapping table each time it is called. For example, if the 2nd row is active at this moment, after mux_map_next instruction call the 3rd row is active. If the mapping table end address is reached, activation rolls to the mapping table start address next time when the mux_map_next instruction is called. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_LD_NEXT

Similar than the mux_map_next instruction, but only the index pointer is set to point to the next row; that is, no mapping is set, and the engine-to-LED-driver connection is not updated.

MUX_MAP_PREV

This instruction sets the previous row active in the mapping table each time it is called. For example, if the 3rd row is active at this moment, after mux_map_prev instruction call the 2nd row is active. If the mapping table start address is reached, activation rolls to the mapping table end address next time the mux_map_prev instruction is called. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_LD_PREV

Similar than the mux_map_prev instruction, but only the index pointer is set to point to the previous row; that is, no mapping is set, and the engine-to-LED-driver connection is not updated.

MUX_MAP_ADDR

Mux_map_addr sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_LD_ADDR

Mux_ld_addr sets the index pointer to point the mapping table row defined by bits [6:0], but the row is not set active.

7.6.6 Branch Instructions

BRANCH

Branch instruction is mainly indented for repeating a portion of the program code several times. Branch instruction loads step number value to program counter. Loop count parameter defines how many times the instructions inside the loop are repeated. The LP5523 supports nested looping; that is, loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32 kHz clock cycles.

INT

Send interrupt to processor by pulling the INT pin down and setting corresponding status bit high. Interrupt can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A.

RST

Rst instruction resets Program Counter register (address 37H, 38H, or 39H) and continues executing the program from the program start address defined in 4C-4E. Instruction takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is 0000H, which is the rst instruction.

END

End program execution. Instruction takes sixteen 32-kHz clock cycles.

TRIGGER

Wait or send triggers can be used to, for example, synchronize operation between the program execution engines. Send trigger instruction takes sixteen 32 kHz clock cycles and wait for trigger takes at least sixteen 32 kHz clock cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait for trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received. (Note: several triggers can be defined in the same instruction.)

External trigger input signal must stay low for at least two 32 kHz clock cycles to be executed. Trigger output signal is three 32 kHz clock cycles long. External trigger signal is active low; that is, when trigger is sent/received the pin is pulled to GND. Send external trigger is masked; that is, the device that has sent the trigger does not recognize it. If send and wait external trigger are used on the same instruction, the send external trigger is executed first, then the wait external trigger.

The LP5523 instruction set includes the following conditional jump instructions: jne (jump if not equal); jge (jump if greater or equal); jl (jump if less); je (jump if equal). If the condition is true, a certain number of instructions are skipped (that is, the program jumps forward to a location relative to the present location). If condition is false, the next instruction is executed.

7.6.7 Arithmetic Instructions

LD

This instruction is used to assign a value into a variable; the previous value in that variable is overwritten. Each of the engines have two local variables, called A and B. The variable C is a global variable.

ADD

Operator either adds 8-bit value to the current value of the target variable, or adds the value of the variable 1 (A, B, C or D) to the value of the variable 2 (A, B, C or D) and stores the result in the register of variable A, B or C. Variables overflow from 255 to 0.

SUB

SUB Operator either subtracts 8-bit value from the current value of the target variable, or subtracts the value of the variable 2 (A, B, C or D) from the value of the variable 1 (A, B, C or D) and stores the result in the register of target variable (A, B or C). Variables overflow from 0 to 255.