米6体育平台手机版

ZHCSOR4 December 2021 LP5862

PRODUCTION DATA

7.6 Timing Requirements

		MIN	NOM	MAX	UNIT
MISC. Timing Requirements
f_OSC	Internal oscillator frequency		31.2		MHz
f_{OSC _ERR}	Device to device oscillator frequency error	–3%		3%
t_{POR_H}	Wait time from UVLO disactive to device NORMAL			500	µs
t_{CHIP_EN}	Wait time from setting Chip_EN (Register) =1 to device NORMAL			100	µs
t_RISE	LED output rise time		10		ns
t_FALL	LED output fall time		15		ns
t_{VSYNC_H}	The minimum high-level pulse width of VSYNC	200			µs
SPI timing requirements
f_SCLK	SPI Clock frequency			12	MHz
1	Cycle time	83.3			ns
2	SS active lead-time	50			ns
3	SS active leg time	50			ns
4	SS inactive time	50			ns
5	SCLK low time	36			ns
6	SCLK high time	36			ns
7	MOSI set-up time	20			ns
8	MOSI hold time	20			ns
9	MISO disable time			30	ns
10	MISO data valid time			35	ns
C_b	Bus capacitance	5		40	pF
I²C fast mode timing requirements
f_SCL	I²C clock frequency	0		400	KHz
1	Hold time (repeated) START condition	600			ns
2	Clock low time	1300			ns
3	Clock high time	600			ns
4	Set-up time for a repeated START condition	600			ns
5	Data hold time	0			ns
6	Data set-up time	100			ns
7	Rise time of SDA and SCL			300	ns
8	Fall time of SDA and SCL			300	ns
9	Set-up time for STOP condition	600			ns
10	Bus free time between a STOP and a START condition	1.3			µs
I²C fast mode plus timing requirements
f_SCL	I²C clock frequency	0		400	KHz
1	Hold time (repeated) START condition	600			ns
2	Clock low time	1300			ns
3	Clock high time	600			ns
4	Setup time for a repeated START condition	600			ns
5	Data hold time	0			ns
6	Data setup time	100			ns
7	Rise time of SDA and SCL			300	ns
8	Fall time of SDA and SCL			300	ns
9	Set-up time for STOP condition	600			ns
10	Bus free time between a STOP and a START condition	1.3			µs

Figure 7-1 SPI Timing Parameters

Figure 7-2 I²C Timing Parameters