When selecting data refresh Mode 1, outputs are refreshed instantly after data is received.

When selecting data refresh Mode 2 and 3, VSYNC signal is required for synchronized display. Programming flow is showed as Figure 9-2. To display full pixel of last frame, VSYNC pulse must be sent to the device after the end of last PWM. Time between two pulses t_SYNC must be larger than the whole PWM time of all Dots t_frame. Common selection like 60 Hz, 90 Hz, 120 Hz or even higher refresh frequency an be supported. High pulse width longer than t_{SYNC_H} is required at the beginning of each VSYNC frame, and data must not be write to PWM registers during high pulse width.