ZHCSO29 July 2021 LP5890
PRODUCTION DATA
In order to simplify the system power rails design, we suggest that VR, VCC use one power rail, and VG, VB use another power rail. Figure 11-1 gives an example for power rails routing.
Connect the GND pin to thermal pad on board with the shortest wire and the thermal pad is connected to GND plane with the vias, as many as possible to help the power dissipation.
Figure 11-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to uniform the current flowing from the line switch to the left side and right side LEDs in white grayscale. With this connection, the unbalance of the parasitic inductor from the routing will be the smallest and the display performance will be better, especially in low grayscale condition.
Figure 11-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the LED path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However, the data transmission sequence should be adjusted to follow the pins routing map. For example, R0 connects to column 15 (LED15 ). The first data should be column 15 (LED15) rather than column 0 (LED0).
Figure 11-4 gives an example for channel routing with pin number sequence. With this connection, the data transmission sequence will be the same with pin number sequence. For example, R0 connects to column 0 (LED0 ). The first data will be column 0 (LED0). However, with this connection, the inductance for each channel may be different, which might bring a slight difference for the worst case.