8.3.1 Enable (EN)

The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the V_EN(ON) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the V_EN(OFF) threshold to ensure that the device is fully disabled and the automatic output discharge is activated.

When the device is disabled the output stage is disabled, the PG output pin is low, and the output automatic discharge is ON.

8.3.2 Output Automatic Discharge (R_AD)

The LP5912-Q1 output employs an internal 100-Ω (typical) pulldown resistance to discharge the output when the EN pin is low. Note that if the LP5912-Q1 EN pin is low (the device is OFF) and the OUT pin is held high by a secondary supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground.

8.3.3 Reverse Current Protection (I_RO)

The LP5912-Q1 input is protected against reverse current when output voltage is higher than the input. In the event that extra output capacitance is used at the output, a power-down transient at the input would normally cause a large reverse current through a conventional regulator. The LP5912-Q1 includes a reverse voltage detector that trips when V_IN drops below V_OUT, shutting off the regulator and opening the PMOS body diode connection, preventing any reverse current from the OUT pin from flowing to the IN pin.

If the LP5912 EN pin is low (the LP5912 is OFF) and the OUT pin is held high by a secondary supply, current flows from the secondary supply through the automatic discharge pulldown resistor to ground. This is not reverse current, this is automatic discharge pulldown current.

Note that reverse current (I_RO) is measured at the IN pin.

8.3.4 Internal Current Limit (I_SC)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate continuously at the I_SC current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

8.3.5 Thermal Overload Protection (T_SD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which allows the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

8.3.6 Power-Good Output (PG)

The LP5912-Q1 device has a power-good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (PG_LTH), the PG pin open-drain output engages (low impedance to GND). When the output voltage rises above the PG threshold voltage (PGV_HTH), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.

The input supply, V_IN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin output status is valid. The PG pin output status is undefined when V_IN is less than 1.6 V.

In power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output voltage rises above the PG_HTH threshold voltage. If the output voltage rises above the PG_HTH threshold and then falls below the PG_LTH threshold voltage the PG pin falls immediately with no delay time.

If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to ground or left floating.

8.4.1 Enable (EN)

The LP5912-Q1 EN pin is internally held low by a 3-MΩ resistor to GND. The EN pin voltage must be higher than the V_EN(ON) threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin voltage is lower than the V_EN(OFF) threshold, the output stage is disabled, the PG pin goes low, and the output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to ground through the internal 100-Ω (typical) output auto discharge pulldown resistance.

8.4.2 Minimum Operating Input Voltage (V_IN)

The LP5912-Q1 device does not include any dedicated UVLO circuit. The device internal circuit is not fully functional until V_IN is at least 1.6 V. The output voltage is not regulated until V_IN has reached at least the greater of 1.6 V or (V_OUT + V_DO).