ZHCSFR8 November 2016 LP5922
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 External Capacitors
- 8.2.2.2 Input Capacitor, CIN
- 8.2.2.3 Output Capacitor, COUT
- 8.2.2.4 Soft-Start and Noise-Reduction Capacitor, CSS/NR
- 8.2.2.5 Feed-Forward Capacitor, CFF
- 8.2.2.6 No-Load Stability
- 8.2.2.7 Power Dissipation
- 8.2.2.8 Estimating Junction Temperature
- 8.2.2.9 Recommended Continuous Operating Area
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP5922 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5922.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5922 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5922 GND pin using as wide and as short of a copper trace as is practical.
Avoid connections using long trace lengths, narrow trace widths, or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions
10.2 Layout Example
Figure 25. LP5922 Typical Layout