| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| OPEN |
SHORT |
VREF_OK |
VBOOST_OK |
OVP |
OCP |
TSD |
UVLO |
|
| NAME |
BIT |
ACCESS |
DESCRIPTION |
| OPEN |
7 |
R |
LED open fault detection |
| 0 = No fault |
| 1 = LED open fault detected. The value is not latched. |
| SHORT |
6 |
R |
LED short fault detection |
| 0 = No fault |
| 1 = LED short fault detected. The value is not latched. |
| VREF_OK |
5 |
R |
Internal VREF node monitor status |
| 1 = VREF voltage is OK. |
|
| VBOOST_OK |
4 |
R |
Boost output voltage monitor status |
| 0 = Boost output voltage has not reached its target (VBOOST < Vtarget – 2.5V) |
| 1 = Boost output voltage is OK. The value is not latched. |
| OVP |
3 |
R |
Overvoltage protection |
| 0 = No fault |
| 1 = Overvoltage condition occurred. Fault is cleared by reading the register 02h. |
| OCP |
2 |
R |
Over current protection |
| 0 = No fault |
| 1 = Overcurrent condition occurred. Fault bit is cleared by reading this register. |
| TSD |
1 |
R |
Thermal shutdown |
| 0 = No fault |
| 1 = Thermal fault generated, 150°C reached. Boost converter and LED outputs are disabled until the temperature has dropped down to 130°C. Fault is cleared by reading this register. |
| UVLO |
0 |
R |
Undervoltage detection |
| 0 = No fault |
| 1 = Undervoltage detected on the VDD pin. Boost converter and LED outputs are disabled until VDD voltage is above the UVLO threshold voltage. Threshold voltage is set with EPROM bits. Fault is cleared by reading this register. |